SPTS Rapier

RESERVATION RULES AND BOOKING FEES POLICY:

1. Maximum allowed booking per person between 9am and 5pm is 2 hours. 
2. Reservation names must correspond to operators.

Contents:

  1. Introduction
  2. Rapier module 
  3. Standard processes
  4. Photos gallery

I. Introduction

SPTS Rapier etcher is an optimized Deep Reactive Ion Etching (DRIE) system for Silicon (Si) and Silicon on Insulator (SOI) wafers. It includes:

    • Single vacuum cassette loader – 25 wafers capacity
    • Brooks Magnatran 7 transport robot
    • A dual high density Inductive Coupled Plasma (ICP) source
    • An Electrostatic Clamping Chuck (ESC) 
    • Radio and low frequencies wafer biasing, with pulsing possibility
    • High speed digital mass flow controllers
    • Amplified optical emission spectroscopy end-point-system
    • White light interferometry end-point system
    • Powerful software with possibility of various ramping curves of all process parameters with time

II. Rapier module

SPTS Rapier module is a unique, patented dual plasma source, that offers high flexibility with multiple operating modes. 

SPTS Rapier module is fitted with two RF independent sources (up to 3kW),  and two independent gas showers (center and edge zones) for excellent uniformity at improved etch rates control.

The module includes a high-efficiency, thick dielectric, bipolar electro-static clamping (ESC) with variable clamp voltage. Temperature control ranges from -10°C to 30°C.  Wafer edge protection is available for critical edge tilt control.

Wafer biasing is possible as radio frequency (up to 2kW) or low frequency (up to 1.2kW), both with pulsing possibility and control of the duty cycle.

Chamber plasma conditioning or self-cleaning can run as wafer-less if needed.

Available process gases are 2x SF6 720sccm, 2x C4F8 500sccm, O2 300sccm & 1000sccm, Ar 500sccm, N2 100sccm. 

III. Standard processes

ProcessEtch rates*Remarks
DRIEAverage 3 to 8um/min.

Trench 2um: 300nm/loop.

Trench >200um: 800nm/loop.
O2 descum step included in recipe: initial PR removal of 300nm.
Slight bowing profile on top.
Notch on SOI <300nm.
PR etch rate 6nm/loop.
SiO2 etch rate 2.5nm/loop.
High Aspect Ratio (HAR)Hole 10um: 200nm/loop.

Trench 2um: 165nm/loop.
SiO2 hard mask required (2.5nm/loop).
Last 300nm of mask not viable because of faceting.
DRIE-NanoTrench 350nm: 150nm/loop.For sub-microns patterns.
Scallops <50nm.
Depth limited to tens of um.
Wafer thinning4.4 um/min.uniformity +/- 3.5%.
* etch rates as design dependent (total surface load as well as local CD). Etch rate typically reduces in time and with increasing aspect ratio of the structure (ARDE).

IV. Photo gallery