Journal Papers

Pre-EKV Developments

  1. H.J. Oguey and S. Cserveny, ‘Modele du transistor MOS valable dans un grand domaine de courants’, Bull. SEW VSE, Feb.1982
  2. H.J. Oguey and S. Cserveny, ‘MOS modelling at low current density’, Summer Course on “Process and Device Modelling,” ESAT Leuven-Heverlee, Belgium, June 1983.
  3. S. Cserveny, ‘Closed Form Expression MOS Transistor Model for Analog Circuit Simulations’ in “LOW POWER DESIGN A Collection of CSEM Papers” edited by E. Vittoz, E Dijkstra and D. Shields for Electronic Design Magazine Books Division in 1995.

Original EKV Paper

  1. C. Enz, F. Krummenacher, E. Vittoz, ‘An analytical MOS transistor model valid in all regions of Operation and dedicated to low-voltage and low-current applications’, Journal on Analog Integrated Circuits and Signal Processsing, Kluwer Academic Publishers, pp. 83-114,  July 1995

Recent Publications

  1. A. Antonopoulos, M. Bucher, K. Papathanasiou, N. Mavredakis, N. Makris, R. Sharma, P. Sakalas, M. Schroter CMOS small-signal and thermal noise modeling at high frequencies IEEE Trans. Electron Devices, 60 (11) (2013), pp. 3726–3733
  2. Makris, N.; Bucher, M., “Temperature scaling of CMOS analog design parameters,” Electrotechnical Conference (MELECON), 2012 16th IEEE Mediterranean , vol., no., pp.187,190, 25-28 March 2012
  3. C. C. Enz, ‘A Short Story of the EKV MOS Transistor Model’, IEEE SSCS, July 2008 On-Line Issue
  4. A. Bazigos, M. Bucher, P. Sakalas, M. Schroter, W. Kraus High-frequency scalable compact modelling of Si RF-CMOS technology Phys. Status Solidi (c), 5 (12) (2008), pp. 3681–368
  5. M. Bucher, A. Bazigos, S. Yoshitomi, N. Itoh, ‘A Scalable Advanced RF IC Design-Oriented MOSFET Model’, Int. Journal of RF and Microwave Computer Aided Engineering, Vol. 18, N° 4, pp. 314-325, 2008
  6. M. Bucher and A. Bazigos, ‘An efficient channel segmentation approach for a large-signal NQS MOSFET model’ Solid-State Electronics, Volume 52, Issue 2, Feb. 2008, pp. 275-281
  7. A. Bazigos, M. Bucher, P. Sakalas, M. Schroter, W. Kraus, ‘High-frequency compact modelling of Si-RF CMOS’, 3rd Int. Conf. on Micro-Nanoelectronics, Nanotechnology and MEMS (Micro&Nano2007), NCSR Demokritos, Athens, Greece, November 18-21, 2007
  8. M. Bucher, D. Diamantakos, A. Bazigos, F. Krummenacher, ‘Design-oriented Characterization and Parameter Extraction Methodologies for the EKV3 MOSFET Model’, NANOTECH 2007 Workshop on Compact Modeling, May 22-24, 2007 Santa Clara, California, USA
  9. Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu and M. Declercq, ‘The HV-EKV MOSFET Model’, CMC Meeting, Boston 8th May 2006
  10. M. Bucher, A. Bazigos, E. Kitonaki, F. Krummenacher; ‘Recent Advances in the EKV3 MOS Transistor Model’; NANOTECH 2006, Workshop on Compact Models, Boston, Massachusetts, May 8-11, 2006
  11. M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, Ch. Enz, “EKV3.0: An Advanced Charge Based MOS Transistor Model”, (Book Chapter 3, p. 67) in W.Grabinski et el Eds, ‘Transistor Level Modeling for Analog/RF IC Design’, ISBN:1-4020-4555-7
  12. M. Bucher, A. Bazigos, F. Krummenacher, J.-M. Sallese, C. Enz , W. Grabinski, ‘Advances in MOSFET Charges Modeling: EKV3.0 MOSFET Model’, NANOTECH 2005 Workshop on Compact Modeling, Anaheim, May 10-12, 2005
  13. J.M. Sallese, F. Krummenacher, F. Prégaldiny, Ch. Lallement, A. Roy and C. Enz “A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism“, Solid-State Electronics, Vol. 49, N° 3, March 2005, pp.485-489
  14. M. Bucher, C. Lallement, F. Krummenacher, C. Enz, “A MOS Transistor Model for Mixed Analog-Digital IC Design,” (Book Chapter 3, p. 47) in R. Reis and J. Jess (Eds.), Design of System on a Chip. Devices & Components. ISBN 1-4020-7928-1, Kluwer Academic Publishers, 2004.
  15. M. Bucher, D. Kazazis, F. Krummenacher, ‘Geometry- and Bias-Dependence of Normalized Transconductances in Deep Submicron CMOS’, NANOTECH 2004 Workshop on Compact Modeling, Boston, March 8-11, 2004
  16. J.M. Sallese, M. Bucher, F. Krummenacher and P. Fazan, “Inversion charge linearization in MOSFET modeling and rigorous derivation of the EKV compact model” Solid-State Electronics, Vol. 47,  N° 4, April 2003, pp. 677-683
  17. E. Vittoz, C.Enz and F.Krummenacher, ‘A Basic Property of MOS Transistors and its Circuit Implications’, NANOTECH 2003 Workshop on Compact Modeling, San Francisco, Feb. 23-27, 2003
  18. C. Lallement, J.-M. Sallese, M. Bucher, W. Grabinski, P. Fazan, “Accounting for Quantum Effects and Polysilicon Depletion from Weak to Strong Inversion in a Charge-Based Design-Oriented MOSFET Model”, IEEE Trans. Electron Devices , Vol. 50, N° 2, pp. 406-417, February 2003
  19. J.-M. Sallese, M. Bucher, F. Krummenacher, P. Fazan, “Inversion Charge Linearization in MOSFET Modeling and Rigorous Derivation of the EKV Compact Model”, Solid-State Electronics, Vol. 47, pp. 677-683, 2003
  20. M. Bucher, D. Kazazis, F. Krummenacher, D. Binkley, D. Foty, Y. Papananos, “Analysis of Transconductances at All Levels of Inversion in Deep Submicron CMOS”, Proc. 9th IEEE Conf. on Electronics, Circuits and Systems (ICECS 2002), Vol. III, pp. 1183-1186, Dubrovnik, Croatia, September 15-18, 2002
  21. C. Lallement, F. Pécheux et Y. Hervé, “A VHDL-AMS Case Study: The Incremental Design of an Efficient 3rd generation MOS Model of Deep Sub Micron Transistor”, SOC Design Methodologies,” Editeurs: M. Robert, B. Rouzeyre, C. Piguet, M. -L. Flottes, Kluwer Academic Publishers, Boston, Hardbound (ISBN 1-4020-7148-5), pp. 349 – 360, July 2002.
  22. M. Bucher, ‘The EKV Compact MOS Transistor Model Version 3: Accounting for Deep-Submicron Aspects’, NANOTECH 2002 Workshop on Compact Modeling, San Juan, Puerto Rico, USA, April 23-25, 2002
  23. W. Grabinski, J.-M. Sallese, M. Bucher, F. Krummenacher, “Compact modelling of ultra deep submicron CMOS devices”, Bulletin of the Polish Academy of Sciences, Vol. 50, Nr. 1, pp. 13-27, 2002. ISSN: 0239-7528
  24. W. Grabinski, ‘EKV v2.6 Parameter Extraction Tutorial‘, ICCAP Users’ Conference, Berlin, March 2002
  25. W. Grabinski, ‘EKV Model v2.6 and Extraction Methodologies’, (webcast), ICCAP Users’ Web Conference, Dec. 2001
  26. C. Lallement, F. Pêcheux, Y. Hervé, ‘VHDL-AMS Design of a MOST Model Including Deep Submicron and Thermal-Electronic Effects‘, 2001 IEEE International Workshop on Behavioral Modeling and Simulation BMAS 2001 October 10-12, 2001, FountainGrove Inn Santa Rosa, California, USA
  27. M. Bucher, J.-M. Sallese, C. Lallement, ‘Accounting for Quantum Effects and Polysilicon Depletion in an Analytical Design-Oriented MOSFET Model‘,  Simulation of Semiconductor Processes and Devices 2001, pp. 296-299, Eds. D. Tsoukalas, C. Tsamis, Springer Vienna, NewYork, ISBN 3-211-83708-6
  28. A.-S. Porret, J.-M. Sallese, C. Enz, ‘A Compact Non-Quasi-Static Extension of a Charge-Based MOS Model‘, IEEE Trans. on ED, Vol. 48, No. 8, pp. 1647- 1654, Aug. 2001
  29. J.-M. Sallese, ‘Advancements in DC and RF MOSFET Modeling with the EPFL-EKV Charge Based Model‘, Special session:  MOS Transistor: Compact Modeling and Standardization Aspects, 8th International Conference MIXDES 2001, Zakopane, Poland, June 21-23, 2001.
  30. W. Grabinski, ‘Compact Modeling of Low-power and RF Analogue MOSFET Devices‘, Special session: Compact Modeling and Standardization Aspects, 8th International Conference MIXDES 2001, Zakopane, Poland, June 21-23, 2001.
  31. D. Binkley, M. Bucher, D. Foty, ‘Design-Oriented Characterization of CMOS over the Continuum of Inversion Level and Channel Length’, Proc. 7th IEEE Int. Conf. on Electronics, Circuits & Systems ICECS’2k, pp. 161-164, Kaslik, Lebanon, Dec. 17-20, 2000.
  32. W. Grabinski, M. Bucher, J.-M. Sallese, F. Krummenacher, ‘Advanced Compact Modeling of the Deep Submicron Technologies’, JTIT vol.3-4/2000 pp.32-42
  33. W. Grabinski, M. Bucher, J.-M. Sallese, F. Krummenacher, ‘Compact Modeling of Ultra Deep Submicron CMOS Devices’, ICSES’2000, October 17-20, 2000, Ustron, Poland.
  34. W. Grabinski, M. Bucher, J.-M. Sallese, F. Krummenacher, ‘Advanced Compact Modeling of the Deep Submicron Technologies’, Diagnostic and Yield, D&Y’2000, June 28-30, 2000, Warsaw, Poland.
  35. F. Krummenacher, M. Bucher, W. Grabinski;  ‘RF EKV MOSFET model implementation’; CRAFT European Project Project N° 25710; WP21; July 28, 2000
  36. F. Krummenacher, M. Bucher, W. Grabinski; ‘HF MOST model validation’; CRAFT European Project Project N° 25710; WP22; July 28, 2000
  37. F. Krummenacher, M. Bucher, W. Grabinski; ‘HF MOSFET model parameter extraction’; CRAFT European Project Project N° 25710; WP23; July 28, 2000
  38. F. Krummenacher, W. Grabinski, M. Bucher, ‘Advances in RF CMOS Modeling Based on the EPFL-EKV Model’, Workshop on RF CMOS Transceivers, Pavia, June 20-21, 2000
  39. J.-M. Sallese, A.-S. Porret, ‘A novel approach to charge-based non-quasi-static model of the MOS transistor valid in all modes of operation’, Solid State Electronics, Volume 44, No 6, pp. 887-894, June 2000.
  40. J.-M. Sallese, M. Bucher, C. Lallement, ‘Improved Analytical Modelling of Polysilicon Depletion for CMOS Circuit Simulation’, Solid State Electronics, Volume 44, No 6, pp. 905-912, June 2000.
  41. W.Grabinski, M. Bucher, F. Krummenacher, ‘Harmonic Distortion Analysis Based on the EPFL-EKV Model’, Silicon RF-IC: Modeling and Simulation Workshop 24-25 February 2000, EPFL, Lausanne, Switzerland
  42. J.-M. Sallese, M. Bucher, C. Lallement, W. Grabinski, ‘Advances in AC Modeling of MOSFET Using EKV Formalism’, Silicon RF-IC: Modeling and Simulation Workshop 24-25 February 2000, EPFL, Lausanne.
  43. M. Bucher, ‘Analytical MOS Transistor Modelling for Analog Circuit Simulation’, Ph.D. Thesis No. 2114 (1999), Swiss Federal Institute of Technology, Lausanne (EPFL).
  44. M. Bucher, J.-M. Sallese, C. Lallement, W. Grabinski, C. C. Enz, F. Krummenacher, ‘Extended Charges Modeling for Deep Submicron CMOS’, Int. Semicond. Device Research Symp. (ISDRS’99), Charlottesville, Virginia, December 1-3, 1999.
  45. F. Krummenacher,  W. Grabinski, M. Bucher, ‘RF MOSFET modeling approach based on the EPFL-EKV model’,  International workshop on low power RF integrated circuits, Lausanne, 19-20 October 1999
  46. W. Grabinski, M. Bucher, F. Krummenacher, ‘The EKV Compact MOSFET Model and its Low-Power Analog and RF Applications’, Proc. XXIInd Nat. Conf. on Circuit Theory and Electronic Networks, KKTOIUE’99, pp. 265-270, Stare Jablonki, Poland, October 20-23, 1999.
  47. W. Grabinski, M. Bucher, F. Krummenacher, ‘The EKV Model Parameter Extraction Based on its IC-CAP USERC Implementation’, HP-IC-CAP Users Meeting, Marseille, France, June 17, 1999.
  48. C. Enz, Y. Cheng, ‘MOS Transistor Modeling Issues for RF Circuit Design’, Workshop on Advances in Analogue Circuit Designs, Nice, March 1999.
  49. M. Bucher, W. Grabinski, ‘EKV MOS Transistor Modelling & RF Application’,  HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999
  50. L. Portmann, C. Lallement, F. Krummenacher, ‘A High Density Integrated Test Matrix of MOS transistors for Matching Study’,  ICMTS 1998. 1998 IEEE International Conference on Microelectronic Test Structures,  Proceedings IEEE, pp.19-24, 1998;
  51. M. Bucher, C. Lallement, C. Enz, F. Théodoloz, F. Krummenacher, ‘Scalable GM/I Based MOSFET Model’ Proc. 1997 Int. Semiconductor Device Research Symposium (ISDRS’97), pp. 615-618, Charlottesville, VA, USA, December 10-13, 1997.
  52. C. Lallement, M. Bucher, C. Enz, ‘Modelling and characterization of non-uniform substrate doping’, Solid-State-Electronics. vol. 41: (12), pp. 1857-1861 Dec. 1997,
  53. C. Enz, E.A. Vittoz, ‘MOS transistor modeling for low-voltage and low-power analog IC design’  Microelectronic Engineering 39: (1-4) 59-76, Sp. Iss. SI Dec. 1997
  54. M. Bucher,  C. Lallement, C. Enz, F. Krummenacher,  ‘Accurate MOS modelling for analog circuit simulation using the EKV model’ 1996 IEEE International Symposium on Circuits and Systems Circuits and Systems Connecting the World, ISCAS 96, pp. 703-6 vol.4, 1996.
  55. C. Lallement, C. Enz, M. Bucher. ‘Simple solutions for modelling the non-uniform substrate doping’, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World, ISCAS 96, pp. 436-9 vol.4, 1996;
  56. M. Bucher, C. Lallement, C. Enz ‘An efficient parameter extraction methodology for the EKV MOST model’, ICMTS 1996. 1996 IEEE International Conference on Microelectronic Test Structures,  Proceedings IEEE, pp.145-50, 1996;
  57. G.A.S. Machado, C. Enz, M. Bucher, ‘Estimating key parameters in the EKV MOST model for analogue design and simulation‘ , 1995 IEEE Symposium on Circuits and Systems IEEE, New York, NY, USA; 3 vol. l+2346 pp. p.1588-91 vol.3. 1995;