Verilog-A implementation of the EPFL-EKV v2.6 model (long channel)
Verilog-A is high level modeling language for writing behavioral models of analog systems. It is an analog-only subset of the Verilog-AMS language, developed by Accellera (formerly known as Open Verilog International – OVI). The complete Verilog-AMS language encompasses both Verilog-A and the well-known Verilog digital language. As of mid-2001, the the Verilog-AMS standard is still undergoing some revisions.
Verilog-AMS is directly competitive with VHDL-AMS. A simulator with VHDL-AMS is now available from Mentor and other software vendors.
Main Verilog-A features:
- Differential-algebraic equations
- Conservative or signal-flow systems
- Mixed disciplines (mechanical, electrical, rotational …) capability
- Parameterization and hierarchy
- Programming structures: loops, if-then-else, assignments, standard math functions
- Analog operators: delay, transition, slew, noise
- Analog events: cross, timer, initial/final steps
Moreover, Verilog-A models can be shared which offers global standardization. Large high-level systems including mixed-discipline and non-electrical systems could be quickly investigated with deeper design exploration.
An example of the EKV Verilog-A code and corresponding netlist are provided below. All model equations are listed in the EKV model documentation [doc]. For Verilog-A syntax details refer to literature [1].
Verilog-A code for the long channel EKV MOSFET model
`include “std.va”
`include “const.va”
// ****************************************************************
// * EKV MOS model (long channel) based on version 2.6 rev.15
// * Function name : ekv26_dc_long for verilog-a implementation
// * The model documetation: http://legwww.epfl.ch/ekv
// ****************************************************************
module ekv(d,g,s,b);
//
// Node definitions
//
inout d,g,s,b ; // external nodes
electrical d,g,s,b ; // external nodes
//
//*** Local variables
//
real x, VG, VS, VD, VGprime, VP;
real beta, n, iff, ir, Ispec, Id;
//
//*** model parameter definitions
//
parameter real L = 10E-6 from[0.0:inf];
parameter real W = 10E-6 from[0.0:inf];
//*** Threshold voltage
// substrate effect parameters (long-channel)
parameter real VTO = 0.5 from[0.0:inf];
parameter real GAMMA = 0.7 from[0.0:inf];
parameter real PHI = 0.5 from[0.2:inf];
//*** Mobility parameters (long-channel)
parameter real KP = 20E-6 from[0.0:inf];
parameter real THETA = 50.0E-3 from[0.0:inf];
analog begin // EKV v2.6 long-channel
VG = V(g, b); VS = V(s, b); VD = V(d, b);
// Effective gate voltage (33)
VGprime = VG – VTO + PHI + GAMMA * sqrt(PHI);
// Pinch-off voltage (34)
VP = VGprime – PHI – GAMMA
* (sqrt(VGprime+(GAMMA/2.0)*(GAMMA/2.0))-(GAMMA/2.0));
// Slope factor (39)
n = 1.0 + GAMMA / (2.0*sqrt(PHI + VP + 4.0*$vt));
// Mobility equation (58), (64)
beta = KP * (W/L) * (1.0/(1.0 + THETA * VP));
// forward (44) and reverse (56) currents
x=(VP-VS)/$vt; iff = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0)));
x=(VP-VD)/$vt; ir = (ln(1.0+exp( x /2.0)))*(ln(1.0+exp( x /2.0)));
// Specific current (65)
Ispec = 2 * n * beta * $vt * $vt;
// Drain current (66)
Id = Ispec * (iff – ir);
//
// Branch contributions to EKV v2.6 model (long-channel)
//
I(d,s) <+ Id;
end // analog
endmodule
Netlist to test Verilog-A EKV model
* EKV long channel MOSFET Model – using Verilog-A
.verilog “ekv.va”
vd 1 0 3
vg 2 0 5
vb 4 0 0
xekv 1 2 0 4 ekv L=20E-6 W=20E-6
.dc vd 0 5 0.1
.end
- D. Fitzpatrick, I. Miller. ‘Analog Behavioral Modeling with the Verilog-A Language’
ISBN 0-7923-8044-4 - OVI Verilog Analog Mixed-Signal Group
- Verilog-2001 Information Page
- IEEE 1076.1 Working Group Analog and Mixed-Signal Extensions to VHDL
- L. Lemaitre, C. McAndrew, S. Hamm, ‘ADMS – Automatic Device Model Synthesizer’, CICC 2002