EKV Users’ Meeting/Workshop

November 4-5, 2004; EPFL in Lausanne

  Agenda  
Sponsors  
IHP ELAN
Technical Program Promoters  
IEEE Swiss
Switzerland		 Top Nano 21
CTI/KTI Associated 		 electrosuisse FSA CM
Modeling Committee
Nov.4, 2004 [13:00 – 17:30] EKV 2.6 Users’ Meeting  
After introducing MEI, we present our experience using the EKV model, first for a low-power (uAmps) analog circuit design, then for other circuits. The challenges of using the EKV model are discussed: model availability, parameter extraction and foundry support. Our experience using of the EKV model and the level of inversion method for general analog circuit design is also discussed. The presentation ends with some questions and discussion items for the workshop.
Giorgio Mugnaini1 and Giuseppe Iannaccone12; 1Universit`a degli Studi di Pisa, 2IEIIT-CNR Pisa
Physics-based analytical model for partially and fully ballistic nanoscale MOSFETs: Double gate, Ultra Thin Body, and Bulk devices
In this work, we present a physics-based analytical model of nanoscale MOSFETs subject to an intermediate regime between drift diffusion and fully ballistic transport. Following the Buttiker virtual probe model of dissipative transport, we demonstrate that for low longitudinal bias a Drift-Diffusion MOSFET is rigorously equivalent to a series of N ballistic MOSFETs, for a suitable N . Moreover, we find that the first N-1 transistors of the ballistic chain can be substituted with a single drift-diffusion MOSFET described by the EKV formalism. The proposed compact macro-model consists of a series of a drift-diffusion section and a ballistic section, that is valid in the complete range of transport regimes comprised between drift-diffusion and fully ballistic, and that reduces to an EKV-like compact model in the limiting cases of drift-diffusion transport. An important aspect is that no smoothing function and no artificial clamp is present in the macromodel. Finally, the proposed analytical description is applicable to Bulk MOSFETs, Double Gate (DG) MOSFETs, and Ultra Thin Body (UTB) SOI MOSFETs, subject to triangular or to rectangular quantum confinement. Our description seamlessly includes Fermi-Dirac statistics, that might be important in UTB devices (<5nm), or at low temperatures.
Ehrenfried Seebacher; AMS
EKV 2.6 implementation and parameter extraction status at austriamicrosystems:

We will give a short overview of the austriamicrosystems CMOS modeling activities, which demonstrate the requirements of a future analog/RF and HV transistor model. The status of the EKV model feasibility study will be presented. We show the implementation in our internal parameter extraction environment for EKV2.6 and present some result for 0.35um and 0.8um process generations. Additionally we will look at some implementations in different state-of-the-art analog simulators. The presentation will end with some inputs for the discussion of next generation MOS models form the analog/RF point of view.

Benoit Mongellaz; Laboratoire IXL
Introduction to Reliability Simulation with EKV Device Model

The development of reliability tool which aims to predict the degradation in circuit performance after a specified operating period is a considerable interest within the semiconductor industry. The tool is based on the capabilities to model wearout failures of MOSFET devices. The advantage to use EKV model are highlighted. Moreover, the experimental means are identified to do reliability experiments and the methods to build EKV reliability model.


Maher Kayal, Danica Stefanovic; EPFL PAD: Procedural Analog Design Tool

Tool Procedural Analog Design tool, abbreviated PAD, is an interactive tool dedicated to the design of analog circuits. The present version covers the design of basic analog structures (one transistor or groups of transistors) and the procedural design of transconductance amplifiers and different operational amplifier topologies. It introduces a new knowledge-based procedural design methodology for analog structures’ sizing that consists of step-by-step design of analog cells by using guidelines for each analog topology. Its interactive interface allows instantaneous visualization of the design tradeoffs. At each step, the user modifies interactively one subset of design parameters and observes the effect on other circuit parameters. At the end, an optimized design is ready for simulation (verification and fine-tuning). PAD embeds a transistor level calculator which uses the complete set of equations of the EKV MOS model. The EKV model is chosen because of its advantages for the design of analog circuits: it links the equations for weak and strong inversion in a continuous way, it has a small number of parameters and a very good accuracy and, finally, large number of transistor parameters, which are important for analog design, can be easily calculated.
In order to make it possible to use PAD tool with both BSIM and EKV input library files, a BSIM to EKV model library file converter is developed as a separate module. BSIM2EKV converter takes BSIM model library file as input, runs an external simulator (PSpice or SMASH) to simulate all required curves and extracts EKV model parameters by fitting to the simulated curves. The extraction algorithm, based on complete EKV model parameter extraction methodology, uses procedural approach to determine EKV model parameters in a specific order respecting the fundaments, as well as the differences of two models. At the end, an EKV model .lib file is generated with the following parameters set: all intrinsic model parameters, temperature parameters, series resistance, 1/f noise parameters, gate overlap capacitances and junction capacitance parameters. For each parameter set, a fitting error is calculated and written to the conversion report file. Furthermore, a set of test bench simulations is provided.


Patrick Martin; CEA
MOSFET Modeling For Low Temperature (77K-200K) Analog Circuit Design

A compact MOSFET model based on the standard EKV 2.6 model is used for analog circuit simulation at low temperature. Device performance at 77 K is studied in this paper for a 0.21 �m CMOS technology with dual polysilicon gate and pocket implants, and conclusions are drawn for the applicability of the low-temperature version of the EKV MOSFET model.

Christophe Lallement, Francois Pecheux, Wladek Grabinski; ENSPS/EPFL
High Level Description of Thermodynamical Effects in the EKV 2.6 MOST Model

We detail and compare two implementations of the same analytical third generation Spice transistor MOST model named EKV 2.6, including thermodynamical interactions. The former implementation has been written in VHDL-AMS and the latter in the Verilog-AMS Hardware Description Language. First, we give some information on the model itself, with its associated thermal network, then we present the features common to VHDL-AMS and Verilog-AMS, and how thermodynamical interaction mechanisms take place into the model. We conclude by giving some simulation results generated by state-of-the-art CAD mixed simulation tools Anacad Advance AMS as well as Mica and Spectre with Verilog-AMS.

Eric Vittoz; EPFL
A Fundamental Property of MOS Transistors

The drain current of a MOS transistor is the (linear) superposition of independent and symmetrical effects of source and drain voltages. This property, its limits as well as the possible reasons for its degradation will be explained, using the EKV approach. The related concept of pseudoresistors will be explained.

Posters:

Bart Desoete, AMIS
Thermal modelling of smart power devices

Thermal effects inside integrated semiconductor devices are affecting device and circuit behaviour significantly, especially for smart power technologies. Therefore an accurate prediction of the internal temperature increase is an important step towards a full electro-thermal model. We have developed a tool which predicts temperature as a function of space and time, based on simplified assumptions and on analytical equations. The tool is much faster than existing software based on numerical methods, is sufficiently accurate, and can easily be used by designers in a flexible way. The results have been verified in various ways. On the one hand, a comparison has been made with a couple of commercial software tools based on the finite-element method. On the other hand, pulsed measurements on DMOS devices have been performed and were used to predict and cross-check temperature increase using models based on the temperature dependence of charge carrier mobility.


Jan Kaplon1, Wladyslaw Dabrowski2; 1CERN, Geneva, 2AGH. Krakow
Analytical noise optimization of the front end amplifiers for silicon detectors using part of the EKV model

We present a fully analytical noise analysis and optimization of the front end amplifier for readout of silicon detectors using EKV parameterization of MOS devices. Using elementary network theory it is possible to calculate the equivalent noise charge (ENC) as a function of the basic transistor parameters like transconductance and gate capacitance. The EKV model offers simple and accurate formulas for the MOS transconductance and intrinsic gate capacitances for arbitrary inversion order, allowing for noise optimization of the front end amplifier in wide range of the input transistor current density. For the noise calculation we use the model proposed by Van der Ziel, but slightly modified for the moderate inversion region applying an EKV approach for the interpolation of the γ parameter between weak and strong inversion. The excess noise observed in short channel devices is modeled by introducing the excess noise factor Γ.


Marek Mierzwinski; Tiburon DA, Santa Rosa, CA
New Capabilities for the Verilog-A EKV Model (slides)

Compiled Verilog-A provides a new and powerful capability for compact device model development and simulator implementation. Verilog-A is a concise, natural language for describing analog behavior. A compiled Verilog-A architecture provides a simple, yet fully capable, means to distribute models to end-users. The work shows how a Verilog-A version of the EKV can easily be used and extended, both in commercial simulators and in parameter extraction programs such as Agilent IC-CAP. Other complex models, such as the BSIM3 are demonstrated as well.

 Nov. 5, 2004 [9:00 – 17:00]
 EKV 3.0 Workshop  

EKV3.0: a Design-Oriented MOSFET Model for Next Generation CMOS

 
Introduction

The EKV3.0 compact MOS transistor model integrates many years of research & development from several university teams in Europe. The EKV3.0 model addresses needs of advanced analog/RF design using most adavanced CMOS technologies including the sub-0.1um era. EKV3.0 is the only model among “Next Generation MOSFET” model candidates that is accompanied by advanced design methods for analog and RF CMOS, and therefore has a special position among other recently developed models. The workshop intends to show:
  • EKV3.0 model description: structure, functionality, effects, parameters.
  • EKV3.0 model benchmarking, parameter extraction and case studies in advanced CMOS.
  • EKV3.0 code standardization, implementation aspects.
  • Advances in R&D: special effects related to advanced CMOS technology, Noise.
  • Novel CMOS device structures, challenges for future model developments.

EKV3.0 Tutorial

This presentation gives a tutorial overview of the EKV3.0 model intended for public-domain. The code development of EKV3.0 is mainly conducted in cooperation among TUC/NTUA and EPFL. Taking advantage of its robust charge-based ideal model, EKV3.0 has a clear hierarchy of modeled effects, reaching from the ideal charge-based model, to the complete scalable model for short/narrow channel devices, as well as high-frequency aspects. Available effects and parameters in EKV3.0 will be discussed. Parameter extraction methods will be presented, as well as example case studies in advanced CMOS technology.

 
Matthias Bucher, Francois Krummenacher
EKV3.0 Charge Model and Extensions

  • Overview of charge model hierarchy
  • Charge modeling aspects — polydepletion/quantum effects
  • Charge-based mobility, velocity saturation & CLM modeling
  • Short & narrow channel effects

Wladek Grabinski
Compact Model Standardization and Implementation Using Verilog-A

The initiative to standardize compact (SPICE-like) modeling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modeling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance while introducing a new compact model to the semiconductor industry in particular going beyond the ITRS Roadmap technological 100nm node. After short introduction to Verilog-A language related procedures and software tools will be presented as well.

 
Antonios Bazigos, Matthias Bucher
EKV3.0 Model Code, Parameters & Case Studies

  • Verilog-A code
  • Model benchmarking
  • List of model parameters and parameter extraction methodology
  • Case studies in various CMOS technologies

Christian Enz, Ananda Roy
Advanced Noise Modeling in EKV

This paper revisits the fundamental theory of thermal noise in the MOS transistor. It is well-known that carrier velocity saturation, carrier heating and, to some extent, channel length modulation degrades the thermal noise of short-channel MOS devices. This degradation is evaluated in terms of the delta thermal noise parameter defined initially by van der Ziel as the ratio between the thermal noise conductance at the drain and the channel conductance at zero VDS bias voltage. For long-channel devices this factor is equal to 2/3. Today, there is still a controversy about what the value of this factor actually is for short-channel devices. Because the above-mentioned effects can compensate each other in the evaluation of delta, some previous works were able to achieve a good match with the measured data. But their explanations and assumptions are not consistent among themselves. Based on a truly physical charge-based model, this paper tries to clarify the contribution of all these different effects on delta. It also highlights the fact that for circuit designers, the real important parameter is not so much the delta factor but rather the ratio of the thermal noise to the transconductance at the same bias point defined as the gamma thermal noise excess factor.

 
Francois Krummenacher
Gate Current Modeling in EKV

The gate tunneling current model developed within the EKV formalism is described. The model is entirely coherent within the EKV charges modeling approach, and features natural partitioning of tunneling current components according to bias conditions of the device.

 
Jean-Michel Sallese, Ananda Roy, Francois Krummenacher, Fabien Pregaldiny, Christophe Lallement, Christian Enz
A Design Oriented Current Model for Symmetrical DG MOSFET: Correlation with the EKV Formalism

Based on an exact analytical solution, we propose a simple and accurate DC model for the current in undoped symmetric DG MOSFETs that aims at giving a comprehensive understanding of the device, especially from the design point of view. In particular, we introduce normalizations for current and charges that in turn lead to very simple relations. Finally, we emphasize the link that exists between this approach and the EKV formalism derived for bulk devices.