EKV Users Publications

  1. Hora, J.A.; Mapula, N.M.; Talagon, E.D.; Bate, M.B.; Berido, R.S.; Palencia, G.F.P., “Design of RF to DC converter in 90nm CMOS technology for ultra-low power application,” HNICEM, 2015 International Conference on, pp.1-6, 9-12 Dec. 2015
  2. Lee, I.; Sylvester, D.; Blaauw, D., “A Constant Energy-Per-Cycle Ring Oscillator Over a Wide Frequency Range for Wireless Sensor Nodes,” in Solid-State Circuits, IEEE Journal of , vol.PP, no.99, pp.1-15, 2016
  3. Petrosyants, K.O.; Kharitonov, IA; Sambursky, L.M.; Bogatyrev, V.N.; Povarnitcyna, Z.M.; Drozdenko, E.S., “Simulation of total dose influence on analog-digital SOI/SOS CMOS circuits with EKV-RAD macromodel,” East-West Design & Test Symposium, 2013 , vol., no., pp.1,6, 27-30 Sept. 2013 
  4. Rios-Salcedo, S.; Medina-Vazquez, A.S.; Davila-Saldivar, C.; Gurrola-Navarro, M.A., “Using the EKV model to describe the DC operation in weak inversion of the multiple-input FGMOS transistor,” Electronics, Communications and Computing (CONIELECOMP), 2013 International Conference on , vol., no., pp.154,157, 11-13 March 2013
  5. Medina-Vazquez, A.S.; Meda-Campana, M.E.; Gurrola-Navarro, M. A.; Becerra-Alvarez, E.C., “EKV-based method for biasing CMOS analog cells using mUltiple-Inputs Floating Gate MOSFETs,” Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012 International Conference on , vol., no., pp.89,92, 19-21 Sept. 2012
  6. Javid, F.; Iskander, R.; Durbin, F.; Louerat, M. -M, “Analog circuits sizing using the fixed point iteration algorithm with transistor compact models,” Mixed Design of Integrated Circuits and Systems (MIXDES), 2012 Proceedings of the 19th International Conference , vol., no., pp.45,50, 24-26 May 2012
  7. Brinson, M.E.; Nabijou, H.; Adaptive EPFL-EKV long and short channel MOS device models for Qucs, SPICE and modelica circuit simulation; MIXDES, 2011 Proceedings of the 18th International Conference Publication Year: 2011 , Page(s): 65 – 70
  8. Ajbl, A.; Pastre, M.; Kayal, M.; Inversion factor based design methodology using the EKV MOS model; MIXDES, 2011 Proceedings of the 18th International Conference Publication Year: 2011 , Page(s): 90 – 94
  9. Chlis, I.; Bucher, M.; PMOS drain-bulk connected loads for Subthreshold Source-Coupled Logic; MIXDES, 2011 Proceedings of the 18th International Conference Publication Year: 2011 , Page(s): 107 – 112
  10. Yakupov, M.; Tomaszewski, D.; Grabinski, W.; Process control monitor based extraction procedure for statistical compact MOSFET modeling, Mixed Design of Integrated Circuits and Systems (MIXDES), 2010 Proceedings of the 17th International Conference Publication Year: 2010 , Page(s): 85 – 90
  11. Tan, L., Hakim, M. M. A., Connor, S., Bousquet, A., White, W. R., Ashburn, P. and Hall, S. Characterisation of CMOS Compatible Vertical MOSFETs with New Architectures through EKV Parameter Extraction and RF Measurement 10th International Conference on ULtimate Integration of Silicon (ULIS), 18-20 March 2009 Aachen, Germany
  12. Leo H. C. Braga, Suzana Domingues, Milton F. Rocha Jr., Leonardo B. Sá, Fernando S. Campos, Filipe V. Santos, Antonio C. Mesquita, Mário V. Silva and Jacobus W. Swart, Layout techniques for radiation hardening of standard CMOS active pixel sensors, Analog Integrated Circuits and Signal Processing, Volume 57, Numbers 1-2 / November, pp.129-139, 2008
  13. Birahim Diagne, Étude et modélisation compacte d’un transistor MOS SOI double-grille dédié à la conception, Thèse PhD  16 Nov. 2007, Université Louis Pasteur, Strasbourg
  14. V. Wang and K. L. Shepard, On-chip transistor characterisation arrays for variability analysis, Electronics Letters, Vol. 43, No. 15, July, 19, 2007
  15. Nicolas Abelé, Design and fabrication of suspended-gate MOSFETs for MEMS resonator, switch and memory applications Thèse EPFL, no 3838 (2007)
  16. Grybos, P.; Idzik, M.; Maj, P.; Noise Optimization of Charge Amplifiers With MOS Input Transistors Operating in Moderate Inversion Region for Short Peaking Times, Nuclear Science, IEEE Transactions on Vol. 54,  No 3,  Part 2,  June 2007, pp. 555 – 560
  17. Sadayuki Yoshitomi; (Invited Paper) Challenges to Accuracy for the Design of Deep-submicron RF-CMOS Circuit; 12th Asia and South Pacific Design Automation Conference, Jan. 23-26 2007, Yokohama, Japan; ASP-DAC 2007, pp. 438 – 441 (citation and slides)
  18. Coyitangiye, Lyse-Aline; Grisel, Richard; Compact Modeling of MOSFET with VHDL-AMS language IEEE Industrial Electronics, IECON 2006 – 32nd Annual Conference on Nov. 2006 pp. 2927 – 2932
  19. J. He, M. Fang, B. Li and Y. Cao, A new analytic approximation to general diode equation, Solid-State Electronics, Vol. 50, N°7-8, July-August 2006, pp. 1371-1374
  20. Y. Weng, A. Doboli, Digital Cell Macromodel with Regular Substrate Template and EKV based MOSFET Model; Proc. GLS VLSI Conference (GLSVLSI), pp. 172-175, 2005.
  21. Henok T. Mebrahtu, Heavy Ion Radiation Effects on CMOS Image Sensors; M.Sc. Thesis, Graduate Programme in Physics and Astronomy, York University, Toronto, Ontario, September 2005
  22. Amine AYED, Hamadi GHARIANI, Mounir SAMET, Design and Optimization of CMOS OTA with gm/Id Methodology using EKV model for RF Frequency Synthesizer Application“. 12th IEEE ICECS, Gammarth, Tunisia, December 11-14th 2005
  23. Stefanovic D. , Kayal M., Pastre M.,  PAD: A New Interactive Knowledge-Based Analog Design Approach, Analog Integrated Circuits and Signal Processing, Volume 42, Number 3, March 2005, pp. 291-299(9)
  24. Knaipp, M.; Rohrer, G.; Minixhofer, R.; Seebacher, E.; Investigations on the High Current Behavior of Lateral Diffused High-Voltage Transistors; Electron Devices, IEEE Transactions on, Volume: 51, Issue: 10, Oct. 2004, pp.: 1711-1720
  25. Martinez-Castillo, J.; Diaz-Sanchez, A.; Torres-Jacome, A.; Murphy-Arteaga, R.S.; Finol, J.L.; BiCMOS opto-electronic reception system for application in high-frequencies Electronics, Communications and Computers, 2004. CONIELECOMP 2004. 14th International Conference on, 16-18 Feb. 2004, pp.214 – 219
  26. Takatori, K. and Flandre D. “Revised EKV model to apply gm/Id methodology to poly-Si TFT analog design”, 11th MIXDES International Conference Mixed Design of Integrated Circuits and Systems; June 2004, Szczecin, Poland
  27. Xunyu Zhu; Hutchens, C.; EKV model extraction for PD SOI MOSFET Region 5 Conference: Annual Technical and Leadership Workshop, 2004 , 2 April 2004 pp.81 – 83
  28. F. P. Cortes, A. Girardi, E. Conrad Jr, L. S. de Paula, S. Bampi; “An Analog Test Chip for Device Modeling and Characterization” PGMICRO MIcroelectronics Program – GME
  29. Cheemavalagu S., Korkmaz P., and Palem K.V., Ultra Low-energy Computing via Probabilistic Algorithms and Devices: CMOS Device Primitives and the Energy-Probability Relationship, International Conference on Solid State Devices and Materials, 2004 
  30. David M. Binkley, “Optimizing Analog CMOS Design from Weak through Strong Inversion”  CISL Seminars Fall 2003
  31. Colinge, J.P.; Park, J.T.; Application of the EKV model to the DTMOS SOI transistor; 2003 International Semiconductor Device Research Symposium, 10-12 Dec. 2003, pp.:264 – 265
  32. Terry, S.C.; Rochelle, J.M.; Binkley, D.M.; Blalock, B.J.; Foty, D.P.; Bucher, M.; Comparison of a BSIM3 and EKV MOSFET model for a 0.5um CMOS process and implications for analog circuit design Nuclear Science, IEEE Transactions on , Volume: 50 Issue: 4 , Aug. 2003 pp.:915 -920
  33. S. Saramad, G. Anelli, M. Bucher , M. Despeisse, P. Jarron, N. Pelloux, A. Rivetti; Modeling of an Integrated Active Feedback Preamplifier in a 0.25um CMOS Technology at Cryogenic Temperatures; IEEE Trans. Nuclear Sciences, NSS 2002, Vol. 50, N° 8, August 2003.
  34. P. O’Connor, J.-F. Pratte, G. De Geronimo; Low noise charge amplifiers in submicron CMOS; Vth International Workshop on Front End Electronics (FEE 2003) Snowmass, CO; July 2, 2003
  35. B. N. Limketkai and R. W. Brodersen, An equation-based method for phase noise analysis, in Proc. IEEE Custom Integrated Circuits Conf., Sept. 2003, pp. 703-706.
  36. P. Martin, M. Bucher , C. Enz; MOSFET Modeling and Parameter Extraction for Low Temperature Analog Circuit Design, 5th European Workshop on Low Temperature Electronics Journal de Physique IV, N° 12, 2002, pp. Pr3-51-56, Les Editions de Physique, Les Ulis, France.
  37. Bendix, P.; Detailed Comparison of the SP2001, EKV, and BSIM3 Models,  Workshop on Compact Modeling, Fifth International Conference on Modeling and Simulation of Microsystems April 22-25, 2002,San Juan, Puerto Rico, U.S.A.
  38. Salimi, K.; Krummenacher, F.; Dehollain, C.; Declercq, M.; Continuous-time CMOS circuits based on multi-tanh linearisation principle Electronics Letters , Volume: 38 , Issue: 3 , 31 Jan 2002 pp.:103 – 104
  39. Vidal E.; Martínez H.; Porta S.; Poveda A.; EKV-Based Nonlinear Analytical Model for the MRC Circuit Analog Integrated Circuits and Signal Processing, April 2002, vol. 31, no. 1, pp. 69-72(4)
  40. Saijets J.; Andersson M.; Åberg M.; A Comparative Study of Various MOSFET Models at Radio Frequencies Analog Integrated Circuits and Signal Processing, October 2002, vol. 33, no. 1, pp. 5-17(13) 
  41. Bradley A. Minch, “A Low-Voltage Mos Cascode Bias Circuit For All Current Levels“, ISCAS 2002 Proceedings
  42. Trond Ytterdal, Snorre Aunet, “Compact Low-Voltage Self-Calibrating Digital Floating-Gate Cmos Logic Circuits“, ISCAS 2002 Proceedings
  43. A. Girardi, F. Paixão Cortes, J. Choi, J. G. Cipriano, S. Bampi; “Parameter Extraction and Optimization for the EKV MOSFET Model” , Forum on Microelectronics and Digital Systems, 2001, Pirenópolis 2001
  44. Salimi, K.; Krummenacher, F.; Dehollain, C.; Declercq, M.; Two-stage high swing fully integrated tunable quadrature sine oscillator Electronics Letters, Volume: 36, Issue: 16, 3 Aug. 2000 pp.:1338 – 1339
  45. Nicolas Donckers, Carlos Dualibe, Michel Verleysen; Design of Complementary Low-Power CMOS Architectures for Looser-take-all and Winner-take-all, MicroNeuro99 proceedings – 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems Granada (Spain), 7-9 April 1999, IEEE Computer Society, ISBN 0-7695-0043-9, pp. 360 – 365
  46. Stockinger M., Sauter T.,Kerö N.; Das EKV-Modell für PSPICE; Austrochip ´97, Linz; 04-09-1997; in: Methoden des Entwurfs und der Verifikation digitaler Systeme, Universitätsverlag Rudolf Trauner, (1997), 3853208266;pp.: 351 – 357.
  47. Gomez-Cipriano, J., A. L., Bampi,S.; “Comparison of the BSIM3 and EKV Model Parameter Extraction Methodologies with a Direct Search Optimization Method “. In.: Workshop IBERCHIP, 3º, México, 19-21 Fevereiro, 1997. Proceedings, Iberchip, 1997, pg. 429-436.
  48. Gomez-Cipriano, J., Bampi, S.; “Application of the SIMPLEX Method for the MOSFET EKV Model Parameter Extraction”. In: III Congreso Internacional de Ingeniería Electrónica, IEEE/Section Peru, Lima, 11-16 Agosto, 1996. Anais. Lima, Peru, PUC & IEEE/Section, 1996.
  49. Gomez-Cipriano, J., Bampi, S.; “MOSFET Parameter Extractions for the EKV Model With a Direct Search Optimization Method”. In: CONGRESSO DA SOCIEDADE BRASILEIRA DE MICROELETRôNICA, 11º, São Paulo, Agosto 02-04, 1996. Anais. São Paulo, SBmicro, 1996, pg. 307-312.
  50. Cipriano, J. G. e Bampi, Sergio; “Um Estudo Experimental de Extração de Parâmetros do Modelo EKV para Baixas Tensões e Baixa Potência”. In: Seminário Brasileiro de Caracterização em Microeletrônica (2º.), Curitiba, Dez 07-08, 1995. Anais. Curitiba, LAC/Copel, 1995