Approximate and Error-tolerant Circuits for Multimedia and Machine Learning

Objective

The concept of error tolerance, i.e. accepting error in a design to save resources, is well known in many abstraction layers. Built on these ideas, approximate computing has emerged as a promising candidate to improve performance and energy efficiency beyond technology scaling.

Designing approximate circuits explores a new trade off, not only by accepting unreliability, but by intentionally introducing errors to save area and power and overcome the limitations of traditional circuit design.

Designing approximate circuits explores a new trade off, not only by accepting unreliability, but by intentionally introducing errors to save area and power and overcome the limitations of traditional circuit design.

With the exploding amount of data being processed in the cloud and on mobile devices, a wide range of applications can trade accuracy without compromising functionality or user experience. In multimedia applications, a small proportion of errors stays imperceptible to humans. Machine-learning applications have also been proven extremely tolerant to approximation.

Research directions

The ICLAB interests on approximate systems cover several research directions:

  • Approximate arithmetic architectures
  • Voltage/frequency over-scaled circuits
  • Reconfigurable hardware

Selected publications

V. Camus, M. Cacciotti, J. Schlachter and C. Enz, “Design of approximate circuits by fabrication of false timing paths: the carry cut-back adder.” IEEE JETCAS, 2018. (Open access & open source)

X. Jiao, V. Camus, M. Cacciotti, Y. Jiang, C. Enz and R. K. Gupta, “Combining structural and timing errors in overclocked inexact speculative adders.” DATE, 2017.

J. Schlachter, V. Camus, K. V. Palem and C. Enz, “Design and applications of approximate circuits by gate-level pruning.” IEEE TVLSI, 2017.

V. Camus, J. Schlachter, M. Gautschi, F. K. Gurkaynak and C. Enz, “Approximate 32-bit floating-point unit design with 53% power-area product reduction.” ESSCIRC, 2016.

V. Camus, J. Schlachter and C. Enz, “A low-power carry cut-back approximate adder with fixed-point implementation and floating-point precision.” DAC, 2016. (Open access)

V. Camus, J. Schlachter and C. Enz, “Energy-efficient inexact speculative adder with high performance and accuracy control. ISCAS, 2015.” (Nominated for best paper award)

J. Schlachter, V. Camus, K. V. Palem and C. Enz, “Automatic generation of inexact digital circuits by gate-level pruning.” ISCAS, 2015.