The Nano-Tera Workshop on the Next Generation MOSFET Compact Models

15-16 December, 2011


The design of integrated circuits strongly relies on the accuracy of the compact models available in the circuit simulators. In this perspective the BSIM group recently proposed the BSIM6 as a new compact model to eventually replace BSIM3, BSIM4 and PSP for next generation bulk CMOS processes. Since BSIM6 is a charge-based model, it uses many of the features that were initially proposed by the EKV charge-based model and particularly its most recent version. Trying to take advantage of the EKV and new BSIM6 similarities, the BSIM research team from University of California, Berkeley, led by Prof. Chenming Hu and the EKV modeling team at EPFL, led by Prof. Christian Enz, decided to collaborate and jointly develop the new BSIM6 compact model. The BSIM EKV partnership has been officially announced by Profs. Hu and Enz at last ESSDERC-ESSIRC Conference during the MOS-AK Workshop. The BSIM EKV public workshop will convene all the BSIM and EKV researchers as well as the experts from the industry to contribute to the workshop to give an update on the latest status of BSIM6 and EKV (and eventually other models as well) to the modeling and designer community. The event will be followed by an internal workshop reserved to the BSIM and EKV teams for discussion and preparation of a workplan for the next year. 


Day 1: 15 December        

Public Workshop

Time Topic
Morning Session: Room CE 105
9:00 Welcome and Workshop Introduction
Giovanni De Micheli, EPFL
9:00 – 9:30 EKV Modeling Roots
Christian Enz, EPFL
9:30 – 10:00 BSIM Modeling Roadmap
Chenming Hu, UC Berkeley
10:00 – 10:30 Coffee Break
10:30 – 11:00 Analog performance of advanced CMOS and EKV3 model
Matthias Bucher, TU Crete
11:00 – 11:30 BSIM6 Symmetric Bulk MOSFET Model
Yogesh Chauhan, UC Berkeley
11:30 – 12:00 BSIM-IMG: Surface Potential based UTBSOI MOSFET Model
M.A. Karim, UC Berkeley
12:00 – 14:00 Lunch
Afternoon Session: Room CE 5
14:00 – 14:30 High-Voltage MOSFET compact modelling 
Antonios BazigosFrancois Krummenacher and Jean-Michel Sallese, EPFL
14:30 – 15:00 Analog modeling requirements for HV CMOS technology
Ehrenfried Seebacher, austriamicrosystems
15:00 – 15:30 Coffee Break
15:30 – 16:00 Double-gate MOSFETs for SOI Technologies 
Jean-Michel Sallese1, Fabien Pregaldiny2 and Christophe Lallement2
1: EPFL  2: University of Strasbourg
16:00 – 16:30 Analytical Modeling of Triple-Gate MOSFET structures
François Lime and Benjamin Iniguez, URV, Tarragona
16:30 – 17:00 Transistor Level EKV Design Methodologies
Marc Pastre and Maher Kayal, EPFL
17:00 – 18:00 Panel Discussion
18:00 Final remarks and Workshop Closing

Day 2 : 16 December

Industrial/Academic Partner Presentations and Internal EKV/BSIM Experts Meeting

Time Topic
Morning Session: Room INF 328
9:00 Workshop Opening (2nd Day)
9:00 – 9:30 BSIM-CMG: Advanced FinFet Model
Sriram Venugopalan, UC Berkeley
9:30 – 10:00 Ultra Low Power: Emerging Devices and their Benefits for Integrated Circuits 
Adrian Ionescu, EPFL
10:00 – 10:30 Coffee Break
10:30 – 11:00 MOSFET Compact Modeling for Circuit Simulation: A Perspective from Industry
Andre Juge, ST Microelectronics, Crolles
11:00 – 11:30 MOSFET Modeling for Ultra Low-Power RF Design
Thierry Taris, University of Bordeaux
11:30 – 12:00 Accurate Design of Mixed-Mode Circuits by using Advanced MOSFET Modeling
Predrag Habas, EM Microelectronic
  Final Remarks
12:00 – 14:00 Lunch
Afternoon Session: Room INF 328
14:00 – 18:00 Internal EKV/BSIM Experts Group Meeting
(Members only)
18:00 End of the workshop