Background
Today, there is a huge variety of integrated electronic solutions for almost any kind of application, and the semiconductor industry is providing a wide set of alternatives in terms of process architectures. The latter have to be accurately described in order to take advantage of their peculiarities for boosting device performance efficiently. Moreover, possible applications include very specific ones, often in extremely harsh conditions i.e. at cryogenic temperatures or undergoing high ionizing radiation doses. The reliability of simulation tools is seldom guaranteed in this cases, and usually designers have to extrapolate standard compact models, or even go for a long prototyping phase. The need for an accurate description of semiconductor devices functioning, strictly linked to their physics is therefore compulsory for exploiting at best their features.
Objective
The objective of the semiconductor device modeling activity is the compact modeling of advanced semiconductor devices with a strong emphasis on the MOS transistor. In the recent years, the focus was mainly on multi-gate MOS transistors and modeling of noise in nanoscale bulk and double-gate MOS transistors. More recently it was reoriented towards the investigation of the impact of the profound changes in nano-scale devices have on their operation in weak and moderate inversion for use in ultra-low-power analog and RF integrated circuits, together with the description of their operation in harsh environments like at cryogenic temperatures and undergoing high ionizing radiation doses.
Directions of Research
- Modeling effects of cryogenic temperature operation regimes on CMOS processes
- Modeling high ionizing radiation dose effects on MOSFETs
- Refine EKV charge-based model for fitting all the variety of CMOS processes