document.location=”https://www.epfl.ch/labs/esl/workshop-on-designing-sustainable-intelligent-systems-at-date-25/”;
2nd Workshop on Designing Sustainable Intelligent Systems: Integrating Carbon Footprint Reduction, TinyML, and RISC-V
As the world advances towards a more interconnected future with smarter sensors and devices, the convergence of embedded Artificial Intelligence (AI), represented by frameworks such as TinyML, open-source hardware architectures like RISC-V, and sustainability considerations, becomes increasingly vital. Designing systems with these three pillars in mind—Carbon Footprint reduction, TinyML, and RISC-V—has profound implications for creating more sustainable and energy-efficient intelligent systems. Closed and proprietary solutions often limit innovation and prevent the integration of eco-friendly practices by restricting access to foundational technologies. In contrast, open-source initiatives within the RISC-V ecosystem empower academia and industry to collaborate on developing energy-efficient solutions that align with global sustainability goals.
This workshop delves into the intersection of these three critical areas:
- Carbon Footprint Reduction: Addressing the urgent need to minimise the environmental impact of digital systems through sustainable design practices.
- TinyML: Leveraging Tiny Machine Learning to enable AI capabilities on resource-constrained devices, optimising performance while reducing energy consumption (particularly on data communication to the cloud or external elements distant from the location where sensing data is collected).
- RISC-V: Utilising the open-source RISC-V architecture to foster innovation in hardware design, allowing for customization and optimization towards energy efficiency.
By integrating these domains, participants will explore how to design and implement intelligent systems that are powerful, efficient, and environmentally responsible.
Key Objectives of the Workshop:
- Interlinking the Three Pillars: Understand how the combination of Carbon Footprint considerations, TinyML, and RISC-V can lead to the development of sustainable intelligent systems.
- Innovative Solutions for Sustainability: Explore methodologies and technologies that reduce energy consumption and environmental impact without compromising system performance.
- Optimization of AI at the Edge: Learn about deploying embedded AI using TinyML on RISC-V platforms to achieve high efficiency in edge computing applications.
- Collaborative Design Practices: Promote interdisciplinary collaboration to share best practices, tools, and techniques for integrating sustainability into system design.
Call for Posters
To improve the discussion possibilities among junior and senior researchers, a Poster Competition is scheduled as a key part of the workshop. We invite submissions on, but not limited to, the following topics:
- Energy-efficient AI at the Edge: Innovations in deploying machine learning models on resource-constrained devices using TinyML to optimize performance and minimize energy consumption.
- Open-source Hardware for Sustainability: Customization and advancements in RISC-V architectures to enable eco-friendly, energy-efficient intelligent systems.
- Carbon Footprint Analysis in Embedded Systems: Methodologies and tools for evaluating and reducing the environmental impact of embedded systems and IoT devices.
- Industrial Applications of Sustainable Embedded Systems: Case studies and solutions showcasing the integration of TinyML for energy-efficient products in commercial sectors such as automotive, industrial automation, and consumer electronics.
A submission can describe a novel scientific result, provide a position statement about a new and relevant problem, or report a case study on practical experiences with a topic from the list above. The submissions should not be formally published in the past. The workshop will have no formal proceedings. Accepted posters can, at the discretion and with the approval of their authors, be published on the workshop’s website.
Author instructions:
Submissions in the form of 1-page PDF file in Pentachart format (possible template available here) should be submitted through EasyChair:
Key dates
| Submission deadline: | February 14, 2025 |
| Acceptance notification: | February 28, 2025 |
| Workshop: | April 2, 2025 – 8.30am-12.00pm |
Registration
This workshop is co-located with the Design, Automation and Test in Europe Conference and will use its registration facilities. Please register through the DATE website. The early-bird deadline is February 13, 2025:
Workshop organizers
Jose Miranda, ESL, EPFL, Switzerland
Andrés Otero, CEI, UPM, Spain
Alfonso Rodríguez, CEI, UPM, Spain
Alessio Burrello, Polytechnic of Turin, Italy
Daniele Jahier Pagliari, Polytechnic of Turin, Italy
Maurizio Martina, Polytechnic of Turin, Italy
Davide Schiavone, OpenHW, Italy
Miguel Peón-Quirós, ESL, EPFL, Switzerland
David Atienza, ESL, EPFL, Switzerland
Workshop co-organizers and main contributors
STM, Italy