To meet performance, power, and area constraints of edge-computing nodes, as well as to validate in-house Intellectual Property cores, we implement System-On-Chips in silicon. To reduce the NRE and increase the versatily of such systems, we implement SoCs based on programmable microcontrollers based on open-source ISA such RISC-V.

Just such a microcontroller, called X-HEEP, is the main IP used in our SoC to bring together research outocomes from the Application, down to the full-custom layer.

HEEPocrates, a tsmc65 implementation of X-HEEP

ML-enabled IoT devices and embedded AI

X-HEEP: an open-hardware RISC-V system-on-chip