We conduct research, at the architecture level, on the design and modeling of fixed-function and reconfigurable accelerators, to address the performance and efficiency limitations of general-purpose computing solutions.

Our hardware accelerator solutions are designed as either open hardware instances or abstract models depending on the domain and technology level. These solutions can be connected as custom functional units or memory-mapped devices.

Analog in Memory Cores

Coarse-Grained Reconfigurable Arrays

Hardware Accelerators for Posit Arithmetic

Sustainable computing for SKAO