gXr5: system-level simulation of RISC-V architectures

While RISC-V has enjoyed both strong functional simulation support via ISA simulators (such as QEMU and Spike) and RTL simulation support (via Chisel and other HDL simulators), it has little support in the realm of full system-level simulators, especially for simulation of Linux-capable systems. This presents a bottleneck in the RISC-V hardware development process, because it is difficult to quickly and reliably prototype and verify the performance of hardware designs for complex high-level applications, such as deep learning.  

To resolve this bottleneck, we are developing gXR5, a Linux-capable full system simulator built into the gem5 system-level architectural simulator and gem5-X. We extend prior work by implementing the RISC-V privileged specification in gem5.  Our contributions include implementing privileged specification instructions and control andstate registers (CSRs), support for user and supervisor privilege modes, a RISC-V compliant MMU capable of processing virtual memory, and ISA devices and interrupters, in addition to creating and configuring a gem5-compatible bootloader, device tree, Linux kernel, and disk image file system


Related Publications

Validating Full-System RISC-V Simulator: A Systematic Approach
Karan Pathak
2023-06-05Conference PaperPublication funded by WiPLASH H2020 (New on-chip wireless communication plane)Publication funded by Fvllmonti ((FETPROACT))