Identification and correction of workload-dependent functional errors at the logic circuit level

Contact persons:

Dr. Miguel Peón-Quirós ([email protected])

Prof. David Atienza ([email protected])

Prof. Francky Catthoor ([email protected])


IMEC, Leuven (Belgium)

The trend to smaller technology nodes will increase the impact of various effects on the timing properties of the circuits. In particular, Bias Temperature Instability (BTI) affects the timing properties of individual transistors along the aging of the circuit. These timing variations may induce timing violations in the behavior of the complete system.

The traditional method for coping with those effects, which consists simply on guaranteeing large enough margins, leads to inefficient worst-case based designs.

At ESL we aim, in collaboration with IMEC, to tackle those issues at two different levels of abstraction. First, we propose a workflow to characterize BTI-induced timing degradations with respect to the typical workload of the system leveraging our experience in the domain of Wireless Sensor Body Networks (WBSNs). This mechanism enables a significant increase of the operating frequency of the circuits while preventing timing violations.

Second, timing violations frequently result in functional errors that can cause the generation of wrong outputs, or may even lead the system to an unstable or inoperative state. In that regard, we are exploring mechanisms for the detection of timing-induced failures and their possible correction with minimal impact on the circuit timing or energy consumption.

The combination of those techniques will produce more efficient and safe systems with improved performance along all their life cycle.


  • [Under submission].