Full-Custom Digital Design

Beyond Moore: Non-Volatile Memory Elements for Biomedical Systems

Master Thesis


Description: Biomedical sensor nodes and implants running for days or even for years on a single cubic-millimeter battery have extremely low power budgets. Aggressive supply voltage scaling leading to near-threshold or even subthreshold circuit operation is widely used in this context to lower both active energy dissipation and leakage power consumption. However, many biomedical systems have long sleep times and only short active periods, in order to acquire, process, and wirelessly transmit a physiological signal once per hour, for example. In this case, the leakage power of memories storing data between active periods quickly dominates the total power budget, as non-retentive circuit parts are usually power-gated during sleep periods.

Instead of following Moore’s law and manufacturing in the most advanced CMOS technologies (“more Moore”), the biomedical design community typically prefers to use mature technology nodes for 1) high reliability; 2) low leakage currents; and 3) low cost. The ultimate goal of this project is to solve the aforementioned leakage-power problem by enhancing mature CMOS with the emerging memristor technology (“beyond Moore”), thereby allowing zero-leakage sleep states.

This project starts with an extensive literature search non-volatile memory elements with emerging resistive devices (memristor, magnetic tunneling junction, phase-change memory). Both memory macrocells (cross-bar arrays) and distributed storage elements like flip-flops and latches shall be considered. The energy cost to write and read these ReRAM devices shall be evaluated and compared to the leakage power of conventional SRAM macrocells and flip-flops/latches, in order to find the minimum sleep time beyond which it starts to pay off energy-wise to use emerging ReRAM technology. Further work then includes the optimization of existing hybrid CMOS-ReRAM memory elements for higher energy efficiency. Energy-efficient current-starved drive circuits and innovative techniques to deal with the famous sneak-current problem in resistive cross-bar arrays are the foremost problems to be investigated.

Prerequisites: Analog & full-custom digital IC design, Cadence

Work Distribution: 30% literature review, 20% comparison & installation of resistive device compact models, 50% analog/custom-digital circuit design & simulation

Supervisors: Pascal Meinerzhagen (TCL), Pierre-Emmanuel Gaillardon (LSI)