All TCL Publications

2019

Journal Articles

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

R. Giterman; A. Bonetti; A. Burg; A. Teman 

Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2019-12-01. Vol. 66, num. 12, p. 2042-2046. DOI : 10.1109/TCSII.2019.2896164.

2019 International Symposium on Low Power Electronics and Design

A. Burg; S. Mukhopdhyay; M. Ziegler 

Ieee Design & Test. 2019-12-01. Vol. 36, num. 6, p. 82-83. DOI : 10.1109/MDAT.2019.2941713.

Conference Papers

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

M. Pons; C. T. Mueller; D. Ruffieux; J-L. Nagel; S. Emery et al. 

2019-01-01. 40th Annual IEEE Custom Integrated Circuits Conference (CICC), Austin, TX, Apr 14-17, 2019.

LDPC Coded Multiuser Shaping for the Gaussian Multiple Access Channel

A. Balatsoukas-Stimming; S. Rini; J. Kliewer 

2019-01-01. IEEE International Symposium on Information Theory (ISIT), Paris, FRANCE, Jul 07-12, 2019. p. 2609-2613.

A Lyra2 FPGA Core for Lyra2REv2-Based Cryptocurrencies

M. van Beirendonck; L-C. Trudeau; P. Giard; A. Balatsoukas-Stimming 

2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019.

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

E. V. Bravo; A. Bonetti; A. Burg 

2019-01-01. IEEE International Symposium on Circuits and Systems (IEEE ISCAS), Sapporo, JAPAN, May 26-29, 2019.

Scalable Boolean Methods in a Modem Synthesis Flow

E. Testa; L. Amaru; M. Soeken; A. Mishchenko; P. Vuillod et al. 

2019-01-01. Design, Automation & Test in Europe Conference & Exhibition (DATE), Florence, ITALY, Mar 25-29, 2019. p. 1643-1648.

Theses

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

A. Bonetti / A. P. Burg; A. S. Teman (Dir.)  

Lausanne, EPFL, 2019. 

2018

Journal Articles

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. 

Ieee Transactions On Circuits And Systems I-Regular Papers. 2018-10-01. Vol. 65, num. 10, p. 3529-3542. DOI : 10.1109/TCSI.2018.2803735.

Design of LDPC Codes for the Unequal Power Two-User Gaussian Multiple Access Channel

A. Balatsoukas-Stimming; A. P. Liavas 

Ieee Wireless Communications Letters. 2018-10-01. Vol. 7, num. 5, p. 868-871. DOI : 10.1109/LWC.2018.2833855.

Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel

A. Balatsoukas-Stimming; A. Burg 

IEEE TRANSACTIONS ON COMMUNICATIONS. 2018. Vol. 66, num. 6, p. 2322-2332. DOI : 10.1109/TCOMM.2017.2771243.

An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

R. Giterman; A. Fish; N. Geuli; E. Mentovich; A. Burg et al. 

IEEE JOURNAL OF SOLID-STATE CIRCUITS. 2018. Vol. 53, num. 7, p. 2136-2148. DOI : 10.1109/JSSC.2018.2820145.

A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture

C. Condo; P. Giard; F. Leduc-Primeau; G. Sarkis; W. Gross 

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. Vol. 65, num. 4, p. 1420-1431. DOI : 10.1109/TCSI.2017.2745902.

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

R. Ghanaatian; A. Balatsoukas-Stimming; T. Muller; M. Meidlinger; G. Matz et al. 

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2018. Vol. 26, num. 2, p. 329-340. DOI : 10.1109/TVLSI.2017.2766925.

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

R. Giterman; A. Fish; A. Burg; A. Teman 

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS. 2018. Vol. 65, num. 4, p. 1245-1256. DOI : 10.1109/TCSI.2017.2747087.

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things

A. Burg; A. Chattopadhyay; K-Y. Lam 

Proceedings Of The IEEE. 2018. Vol. 106, num. 1, p. 38-60. DOI : 10.1109/Jproc.2017.2780172.

Fast Low-Complexity Decoders for Low-Rate Polar Codes

P. Giard; A. K. Balatsoukas Stimming; G. Sarkis; C. Thibeault; W. J. Gross 

Journal of Signal Processing Systems. 2018. Vol. 90, num. 5, p. 675–685. DOI : 10.1007/s11265-016-1173-y.

Conference Papers

Non-Linear Digital Self-Interference Cancellation for In-Band Full-Duplex Radios Using Neural Networks

A. Balatsoukas-Stimming 

2018-01-01. IEEE 19th International Workshop on Signal Processing Advances in Wireless Communications (SPAWC), Kalamata, GREECE, Jun 25-28, 2018. p. 1-5.

Fast-SSC-Flip Decoding of Polar Codes

P. Giard; A. Burg 

2018. DOI : 10.1109/WCNCW.2018.8369026.

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

A. Bonetti; J. Constantin; A. S. Teman; A. P. Burg 

2018. IEEE International Symposium on Circuits and Systems (ISCAS), Florence, ITALY, May 27-30, 2018.

2017

Journal Articles

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gurkaynak et al. 

Ieee Micro. 2017. Vol. 37, num. 5, p. 20-31. DOI : 10.1109/MM.2017.3711645.

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. Bonetti; C. Thibeault et al. 

IEEE Journal on Emerging and Selected Topics in Circuits and Systems. 2017. Vol. 7, num. 4, p. 616-629. DOI : 10.1109/JETCAS.2017.2745704.

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

A. Bonetti; A. S. Teman; P. Flatresse; A. P. Burg 

IEEE Transactions on Circuits and Systems I: Regular Papers. 2017. Vol. 64, num. 9, p. 2388-2400. DOI : 10.1109/TCSI.2017.2698138.

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

A. Bonetti; N. A. Preyss; A. S. Teman; A. P. Burg 

ACM Transactions on Design Automation of Electronic Systems. 2017. Vol. 22, num. 4. DOI : 10.1145/3054744.

An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems

J. Constantin; R. Houlmann; N. Preyss; N. Walenta; H. Zbinden et al. 

Journal Of Signal Processing Systems For Signal Image And Video Technology. 2017. Vol. 86, num. 1, p. 1-15. DOI : 10.1007/s11265-015-1086-1.

Conference Papers

Blind detection of polar codes

P. Giard; A. K. Balatsoukas Stimming; A. P. Burg 

2017. IEEE International Workshop on Signal Processing Systems (SiPS), Lorient, France, October 3-5, 2017. DOI : 10.1109/SiPS.2017.8109977.

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

A. K. Balatsoukas Stimming; P. Giard; A. P. Burg 

2017. IEEE Wireless Communications and Networking Conference (WCNC), San Francisco, CA, USA, Mar. 2017. p. 1-6. DOI : 10.1109/WCNCW.2017.7919106.

Theses

High-Speed Wireline Link Design

H. Yüksel / A. P. Burg; T. Toifl (Dir.)  

Lausanne, EPFL, 2017. 

Talks

Polar codes and APSK modulation – Just good friends

N. A. Preyss; P. Giard; A. K. Balatsoukas Stimming; A. P. Burg 

Information Theory and Applications Workshop (ITA), San Diego, CA, USA, Feb. 12-17, 2017.

2016

Journal Articles

Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments

M. Yousefbeiki; A. C. M. Austin; J. R. Mosig; A. Burg; J. Perruisseau-Carrier 

Ieee Transactions On Antennas And Propagation. 2016. Vol. 64, num. 12, p. 5131-5145. DOI : 10.1109/Tap.2016.2624138.

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

A. Teman; D. Rossi; P. Meinerzhagen; L. Benini; A. Burg 

Acm Transactions On Design Automation Of Electronic Systems. 2016. Vol. 21, num. 4, p. 59. DOI : 10.1145/2890498.

Synthesis of Dual Mode Logic

L. Moyal; I. Levi; A. Teman; A. Fish 

Integration-The Vlsi Journal. 2016. Vol. 55, p. 246-253. DOI : 10.1016/j.vlsi.2016.07.004.

Wireless Channel Characterization in Burning Buildings Over 100-1000 MHz

A. C. M. Austin 

Ieee Transactions On Antennas And Propagation. 2016. Vol. 64, num. 7, p. 3265-3269. DOI : 10.1109/Tap.2016.2562671.

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

L. Atias; A. Teman; R. Giterman; P. Meinerzhagen; A. Fish 

Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. Vol. 24, num. 8, p. 2622-2633. DOI : 10.1109/Tvlsi.2016.2518220.

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

C. Senning; G. Karakonstantis; A. Burg 

Journal Of Signal Processing Systems For Signal Image And Video Technology. 2016. Vol. 85, num. 1, p. 129-142. DOI : 10.1007/s11265-015-1003-7.

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

O. Andersson; B. Mohammadi; P. Meinerzhagen; A. Burg; J. N. Rodrigues 

Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. Vol. 63, num. 6, p. 806-817. DOI : 10.1109/Tcsi.2016.2537931.

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

N. Edri; P. Meinerzhagen; A. Teman; A. Burg; A. Fish 

Ieee Transactions On Circuits And Systems I-Regular Papers. 2016. Vol. 63, num. 2, p. 222-232. DOI : 10.1109/Tcsi.2015.2512706.

An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs

S. Brenna; A. Bonetti; A. Bonfanti; A. Lacaita 

Integration, the VLSI Journal (Elsevier). 2016. Vol. 53, num. March 2016, p. 88-99. DOI : 10.1016/j.vlsi.2015.12.005.

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

R. Giterman; A. Teman; P. Meinerzhagen; L. Atias; A. Burg et al. 

Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2016. Vol. 24, num. 1, p. 358-362. DOI : 10.1109/TVLSI.2015.2394459.

Conference Papers

A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code

P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. P. Burg; C. Thibeault et al. 

2016. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, Nov. 2016. p. 1194-1198. DOI : 10.1109/ACSSC.2016.7869561.

High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding

H. Yueksel; G. Cherubini; R. D. Cideciyan; S. Furrer; A. Burg et al. 

2016. IEEE Conference on Standards for Communications and Networking (CSCN), Berlin, GERMANY, OCT 31-NOV 02, 2016.

Hardware Decoders for Polar Codes: An Overview

P. Giard; G. Sarkis; A. Balatsoukas-Stinning; Y. Fan; C-Y. Tsui et al. 

2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 149-152.

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

J. Constantin; A. Burg; Z. Wang; A. Chattopadhyay; G. Karakonstantis 

2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, TX, JUN 05-09, 2016. DOI : 10.1145/2897937.2696095.

A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. 

2016. 46th European Solid-State Device Research Conference (ESSDERC) / 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, SWITZERLAND, SEP 12-15, 2016. p. 309-312.

Approximate Computing for Unreliable Silicon

A. P. Burg 

2016. 11th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Partitioned Successive-Cancellation List Decoding Of Polar Codes

S. A. Hashemi; A. Balatsoukas-Stimming; P. Giard; C. Thibeault; W. J. Gross 

2016. IEEE International Conference on Acoustics, Speech, and Signal Processing, Shanghai, PEOPLES R CHINA, MAR 20-25, 2016. p. 957-960.

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

R. Giterman; A. Teman; P. Meinerzhagen; A. Fish; A. Burg 

2016. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, CANADA, MAY 22-25, 2016. p. 1006-1009.

A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination

R. Ghanaatian Jahromi; P. Whatmough; J. H-F. Constantin; A. S. Teman; A. P. Burg 

2016. 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, May 22-25, 2016. p. 2667-2670.

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gürkaynak et al. 

2016. 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), Yokohama, Japan, April 20-22, 2016. DOI : 10.1109/CoolChips.2016.7503670.

Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers

A. Austin; A. K. Balatsoukas Stimming; A. Burg 

2016. 17th IEEE International workshop on Signal Processing Advances in Wireless Communications, Edinburgh, Scotland, UK, July 3-6, 2016.

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

J. H-F. Constantin; A. Bonetti; A. S. Teman; T. C. Müller; L. F. Schmid et al. 

2016. 42nd European Solid-State Circuits Conference (ESSCIRC), Lausanne, Switzerland, September 12-15, 2016. p. 261-264.

Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency

O. Afisiadis; A. C. M. Austin; A. K. Balatsoukas Stimming; A. Burg 

2016. IEEE 83rd Vehicular Technology Conference, Nanjing, China, 15-18 May.

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

J. H-F. Constantin; Z. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg 

2016. 53rd ACM/EDAC/IEEE Design Automation Conference (DAC), Austin, Texas, USA, June 5-9, 2016. p. 13:1-13:6. DOI : 10.1145/2897937.2898095.

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

L. G. Duch; P. Garcia del Valle; S. Ganapathy; A. P. Burg; D. Atienza Alonso 

2016. Design, Automation and Test in Europe Conference (DATE ’16), Dresden, Germany, March 14-18, 2016. p. 838-841.

Theses

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

J. H-F. Constantin / A. P. Burg; D. Atienza Alonso (Dir.)  

Lausanne, EPFL, 2016. 

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

A. K. Balatsoukas Stimming / A. P. Burg (Dir.)  

Lausanne, EPFL, 2016. 

Modulation, Coding, and Receiver Design for Gigabit mmWave Communication

N. A. Preyss / A. P. Burg (Dir.)  

Lausanne, EPFL, 2016. 

2015

Journal Articles

Performance estimation for indoor wireless systems using FDTD method

A. Austin 

Electronics Letters. 2015. Vol. 51, num. 17, p. 1376-1378. DOI : 10.1049/el.2015.1093.

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

H. Kroell; S. Zwicky; B. Weber; C. Roth; D. Tschopp et al. 

Ieee Journal Of Solid-State Circuits. 2015. Vol. 50, num. 7, p. 1690-1701. DOI : 10.1109/Jssc.2015.2417802.

LLR-Based Successive Cancellation List Decoding of Polar Codes

A. Balatsoukas-Stimming; M. B. Parizi; A. Burg 

Ieee Transactions On Signal Processing. 2015. Vol. 63, num. 19, p. 5165-5179. DOI : 10.1109/Tsp.2015.2439211.

Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression

A. Balatsoukas-Stimming; A. Austin; P. Belanovic; A. Burg 

EURASIP Journal on Wireless Communications and Networking. 2015. Vol. 2015, num. 142. DOI : 10.1186/s13638-015-0350-1.

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

M. Owaida; G. Falcao; J. Andrade; C. Antonopoulos; N. Bellas et al. 

Acm Transactions On Embedded Computing Systems. 2015. Vol. 14, num. 2. DOI : 10.1145/2656207.

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

A. Teman; R. Visotsky 

Ieee Transactions On Very Large Scale Integration (Vlsi) Systems. 2015. Vol. 23, num. 10, p. 2034-2042. DOI : 10.1109/TVLSI.2014.2358699.

Conference Papers

An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes

J. M. Wüthrich; A. K. Balatsoukas Stimming; A. P. Burg 

2015. 2015 IEEE International Conference on Electronics, Circuits, and Systems, Cairo, Egypt, December 6-9, 2015.

Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems

N. A. Preyss; A. Burg 

2015. 2015 22nd IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Cairo, Egypt, December 06-09, 2015. p. 637-640.

Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication

N. Preyss; S. Rodriguez Egea; A. Burg 

2015. 49th Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 8-11, 2015.

A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm

N. A. Preyss; C. C. S. D. Senning; A. P. Burg; W-C. Liu; C-Y. Liu et al. 

2015. 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), Xiamen, Fujian, China, November 9-11, 2015. p. 193-196.

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

S. Brenna; L. Bettini; A. Bonetti; A. Bonfanti; A. Lacaita 

2015. IEEE Nordic Circuits and Systems Conference (NORCAS), Oslo, October 2015. DOI : 10.1109/NORCHIP.2015.7364387.

Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation

A. Austin; O. Afisiadis; A. Balatsoukas-Stimming; A. Burg 

2015. 16th ACM International Symposium on Mobile Ad Hoc Networking and Computing, Hangzhou, China, 22-25 06 2015. p. 407-408. DOI : 10.1145/2746285.2764932.

Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication

N. A. Preyss; L. Koester; A. P. Burg 

2015. Midwest Symposium on Circuits and Systems, Fort Collins, Colorado, USA, August 2-5, 2015.

Approximate Computing With Unreliable Dynamic Memories

S. Ganapathy; A. S. Teman; R. Giterman; A. P. Burg; G. Karakonstantis 

2015. International New Circuits And Systems Conference (NEWCAS), Grenoble, France, June 7-10, 2015.

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

A. S. Teman; G. Karakonstantis; A. P. Burg; R. Giterman; P. A. Meinerzhagen 

2015. DATE 2015, Grenoble, France, March 9-13, 2015.

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

S. Ganapathy; G. Karakonstantis; A. S. Teman; A. P. Burg 

2015. Design Automation Conference (DAC’15), San Francisco, California, USA, June 7-11, 2015. p. 1-6. DOI : 10.1145/2744769.2744871.

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

A. Bonetti; A. S. Teman; A. P. Burg 

2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7169017.

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

P. A. Meinerzhagen; A. Bonetti; G. Karakonstantis; C. Roth; F. K. Gürkaynak et al. 

2015. IEEE International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, May, 2015. DOI : 10.1109/ISCAS.2015.7168911.

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

J. H-F. Constantin; L. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg 

2015. The Design, Automation and Test in Europe (DATE), Grenoble, France, March 9-13, 2015.

Posters

Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors

A. Bonetti; J. H-F. Constantin; A. S. Teman; A. P. Burg 

Nanotera Annual Meeting 2015, Bern, Switzerland, May 5, 2015.

Patents

Method and apparatus for low complexity spectral analysis of bio-signals

G. Karakonstantis; A. Sankaranarayanan; A. Burg; S. Murali; D. Atienza Alonso 

US9760536; US2015220486; EP2884884; WO2014027329.

2015.

Student Projects

Power analysis and optimization of on-board processing for the EFM32 microprocessor

A. Gianarda 

2015.

Automated Performance Characterization of Dynamic Clock Adjustment Techniques on an OpenRISC ISS

B. Steinmann 

2015.

2014

Journal Articles

Energy Efficiency through Significance-Based Computing

D. S. Nikolopoulos; H. Vandierendonck; N. Bellas; C. D. Antonopoulos; S. Lalis et al. 

Computer. 2014. Vol. 47, num. 7, p. 82-85.

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

A. Balatsoukas-Stimming; A. J. Raymond; W. J. Gross; A. Burg 

Ieee Transactions On Circuits And Systems Ii-Express Briefs. 2014. Vol. 61, num. 8, p. 609-613. DOI : 10.1109/Tcsii.2014.2327336.

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

H. Dagan; A. Shapira; A. Teman; A. Mordakhay; S. Jameson et al. 

Ieee Journal Of Solid-State Circuits. 2014. Vol. 49, num. 9, p. 1942-1957. DOI : 10.1109/Jssc.2014.2323352.

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

I. Kazi; P. Meinerzhagen; P-E. Gaillardon; D. Sacchetto; Y. Leblebici et al. 

IEEE Transactions on Circuits and Systems Part 1 Regular Papers. 2014. Vol. 61, num. 11, p. 3155-3164. DOI : 10.1109/TCSI.2014.2334891.

Conference Papers

Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes

A. Balatsoukas-Stimming; G. Karakonstantis; A. Burg 

2014. IEEE International Symposium on Information Theory (ISIT), Honolulu, HI, JUN 29-JUL 04, 2014. p. 2977-2981.

Single event upset mitigation in low power SRAM design

L. Atias; A. Teman; A. Fish 

2014. 2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel (IEEEI), Eilat, Israel, 3-5 December 2014. p. 1-5. DOI : 10.1109/EEEI.2014.7005796.

Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers

C. Senning; M. Mendicute; A. Burg 

2014. [IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)’, u’IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)’].

Robust Asynchronous Indoor Localization Using Led Lighting

G. Kail; P. Maechler; N. Preyss; A. Burg 

2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.

Correlation Based Phase Noise Compensation in 60 GHz Wireless Systems

N. A. Preyss; R. Pantic; A. P. Burg 

2014. 2014 IEEE 28-th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December, 3-5, 2014.

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

A. Teman 

2014. 2014 IEEE Faible Tension Faible Consommation (FTFC), Monaco, Monaco, 4-6 May 2014. p. 1-5. DOI : 10.1109/FTFC.2014.6828617.

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

R. Giterman; A. Teman; P. Meinerzhagen; A. Burg; A. Fish 

2014. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, Australia, 1-5 June 2014. p. 2177-2180. DOI : 10.1109/ISCAS.2014.6865600.

Variability-Aware Design Space Exploration of Embedded Memories

S. Ganapathy; G. Karakonstantis; R. Canal; A. P. Burg 

2014. 28th IEEE Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, December 3-5, 2014.

A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead

R. Braojos Lopez; I. Beretta; J. H-F. Constantin; A. P. Burg; D. Atienza Alonso 

2014. The 12th IEEE International Conference on Embedded and Ubiquitous Computing, Milan, 25-29.08.2014.

Theses

Energy Efficient VLSI Circuits for MIMO-WLAN

C. C. S. D. Senning / A. P. Burg (Dir.)  

Lausanne, EPFL, 2014. 

Posters

Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams

L. Amarù; A. Balatsoukas Stimming; P-E. Gaillardon; A. Burg; G. De Micheli 

University Booth at DATE 2014, Dresden, Germany, March 24-28, 2014.

Cross-Layer Inexact Design for Low-Power Applications

V. Camus; G. Karakonstantis; J. Schlachter; A. P. Burg; C. Enz 

NanoTera Annual Meeting, Lausanne, Switzerland,

Patents

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

A. Y. Dogan; J. Constantin; A. Burg; D. Atienza Alonso 

WO2013136259; WO2013136259.

2014.

Student Projects

Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform

E. A. Pignat 

2014.

Low Power Wake-up Receiver

L. F. Schmid 

2014.

RSS Range Estimation for Indoor Localization Using LED Lighting

J. Liu 

2014.