Contact: Ludovic Thomas
Background:
Time-sensitive networks are used for safety-critical systems in planes, satellites or even power plants. Their significance has been increasing over the years and they are now used in many more applications, ranging from autonomous cars, automated manufacturies (industry 4.0) to 5G backbone networks. While traditional public networks aim at improving the mean service performances (mean ping, mean throughput), time-sensitive networks provide guarantees for the worst case (e.g. guarantee of a maximal latency, guarantee of a minimal throughput, guarantee of no loss, …).
To achieve such guarantees, working groups of the IEEE (Institute of Electrical and Electronics Engineers) and the IETF (Internet Engineering Task Force) have been developing technologies. One of them is known as traffic shaping: specific hardware elements, called `regulators’, are placed at the output ports of routers. They enforce the traffic of flows to respect a given contract (in terms of burst and rate), delaying packets if required. Analyses of regulators using Network Calculus [1] have proved that they do not increase the End-To-End latency bounds. On the contrary, deploying regulators at each router within a network tends to reduce the maximum latencies and bursts. This effect is significant when the network is highly loaded.
Regulators do not need to share the same notion of time (they don’t need to be synchronized). However, the mentioned analyses assume that they share the same notion of a duration: 1 second on a device also means 1 second on another device. In the real world, this assumption does not hold. Indeed, the oscillator within a clock may have a frequency slightly different from its nominal one. When this happens, a regulator may enforce a slightly different contract than the one it has been configured with. In a recent work, we have captured this phenomenon in a simplified clock model and we have tried to prove that the good properties of regulators continue to hold. Surprisingly, we have, on the contrary, found a situation in which a specific type of regulators (called the Interleaved Regulator) is unstable within our time model (ie the flows crossing the device have an unbounded latency). Moreover, the instability holds even if the clocks are extremely stable and even if a synchronization protocol is used within the network.
In this project:
The question we propose to answer in this project is whether the found instability is due to our clock model being too simplified or whether it is a fundamental issue of traffic shaping. To achieve this goal, we will use recent published work on clock modelling to simulate the possible evolution of a clock, as well as its interactions with the device it is installed in and the regulators it controls. Using this, we will then perform a network simulation and we will try to find an adversarial case that triggers the instability.
The project can be tailored for both a semester project and a master project.
Project Goals:
- Construct simplified models of some network components such as a source, a regulator.
- Define how these components interact with their respective clock and define an interface with a clock model.
- Thanks to discussions with the SmartGrid team, select, among the literature, a representative clock modelling and add it to the modeled network elements.
- Use all the above constituents to simulate a network with imperfect asynchronous clocks, and find an adversarial situation that leads to unbounded latency.
- Model a synchronization algorithm and its interactions with the different clocks and use it to simulate a network with synchronized clocks.
Student profile
- Programming capabilities in any language suitable for performing simulations (Matlab/Python/C/C++/Java/…)
- Interest in networks, communications or real-time systems would be a plus.
References