Near memory computing


This project aims at creating SRAM boosted with computational capabilities leveraging Near Memory Computing designs

Keywords
#sram #nearmemorycomputing #inmemorycomputing #edgecomputing

Team

  Ansaloni Giovanni
  Atienza Alonso David
  Caon Michele
  Choné Clément Renaud Jean
  Eggermann Grégoire Axel
  Kodra Riselda
  Schiavone Pasquale Davide
  Xu Weihong

Sources of Funding

ACCESS
Fvllmonti


Creation and integration of NMC IPs for edge-computing devices



Related Publications

Crossing the Layers and Dotting the Details: Systematic Exploration of Near-Memory Computing
Kodra, Riselda; Medina Morillas, Rafael; Zapater Sancho, Marina; Atienza, David; Ansaloni, Giovanni
2026-04ISQED'26 The 27th International Symposium on Quality Electronic DesignPublication funded by ACCESS (AI Chip Center for Emerging Smart Systems, sponsored by InnoHK funding, Hong Kong SAR)Publication funded by SwissChips (SwissChips - State Secretariat for Education, Research and Innovation)Publication funded by Edge Companions (Hardware/Software Co-Optimization Toward Energy-Minimal Health Monitoring at the Edge)Publication funded by Cerberus (Addressing the efficiency bottlenecks that prevent edge computing stakeholders from unleashing their full potential.)
Keep All in Memory with Maxwell: a Near-SRAM Computing Architecture for Edge AI Applications
Eggermann, Grégoire Axel; Ansaloni, Giovanni; Atienza Alonso, David
2025-04-25International Symposium on Quality Electronic DesignPublication funded by SwissChips (SwissChips - State Secretariat for Education, Research and Innovation)Publication funded by Edge Companions (Hardware/Software Co-Optimization Toward Energy-Minimal Health Monitoring at the Edge)
Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
Caon, Michele; Choné, Clément Renaud Jean; Schiavone, Pasquale Davide; Levisse, Alexandre Sébastien Julien; Masera Guido; Martina Maurizio; Atienza Alonso, David
2025-04-01IEEE Transactions on Emerging Topics in ComputingPublication funded by SwissChips (SwissChips - State Secretariat for Education, Research and Innovation)
A 16-bit Floating-Point Near-SRAM Architecture for Low-power Sparse Matrix-Vector Multiplication
Eggermann, Grégoire Axel; Rios, Marco Antonio; Ansaloni, Giovanni; Atienza Alonso, David
2023-10-18Conference PaperPublication funded by Fvllmonti (Ferroelectric Vertical Low energy Low latency low volume Modules fOr Neural network Transformers In 3D)Publication funded by ACCESS (AI Chip Center for Emerging Smart Systems, sponsored by InnoHK funding, Hong Kong SAR)