Ultrasound Imaging

LTS5 research in ultrasound imaging

Regularization methods in ultrasound imaging

In terms of acoustic wave propagation, ultrasound imaging poses an inverse problem which relates the tissue reflectivity (image under scrutiny) to the backscattered echoes (the measurements). Standard imaging methods are based on a well-known algorithm called Delay-and-sum (DAS). The major advantage of DAS is that it is fast and highly parallelizable. Its main drawback is that it is an inaccurate solution of the inverse problem which leads to low-quality images. One research topic in LTS5 consists in exploring alternatives to DAS mainly based on regularization approaches. The idea is to inject prior knowledge (sparsity of the image in a well-chosen model) about the tissue reflectivity in order to leverage the ill-posedness of the problem. The problem is recast as a convex optimization algorithm and solved using standard algorithms such as ADMM, primal-dual forward backward or FISTA.

        

Figure: Cyst image reconstructed with the DAS algorithm (left) and with the sparse regularization approach (right).

Compressed sensing and deep learning in ultrasound imaging

Compressed sensing or compressive sensing (CS) is a well-known mathematical framework which ensures perfect recovery of compressible signals from random projections with fewer samples than Nyquist rate. The recovery is achieved by solving a convex optimization problem where the most compressible solution which fits to the measurements is identified. This framework has been substantially studied in the last ten years and has lead to great successes such as: the Rice single pixel camera or the Sparse MRI. At LTS5, we are currently working on applying the CS framework to ultrasound imaging. The first idea is to exploit the intrinsic structure of US data which can be modelled as a stream of pulses, compressible in a redundant dictionary made of shifted replica of the ultrasound pulse. The second idea consists in designing acquisition schemes that are most suited to the CS framework. The last work focuses on designing efficient reconstruction algorithms. To do so, we are intensively working on deep learning algorithms which are becoming extremely popular nowadays due to their ability to perform a various of tasks (object recognition, classification, text generation, image colorization etc.). At LTS5, we are currently focusing on three main deep neural netwrok architectures for ultrasound imaging:

  • DNN that maps convex optimization algorithms such as Fast-Iterative thredsholding algorithm (FISTA);
  • Fully connected architectures (Stacked denoising autoencoders, Multi-layer perceptron);
  • Convolutional neural networks.

High Precision Capacitive Moisture Sensor for Polymers: Modeling and Experiments

R. M. Dos Santos; J-M. Sallese; M. Mattavelli; A. S. Nunes; C. Dehollain et al. 

IEEE Sensors Journal. 2020-03-15. Vol. 20, num. 6, p. 3032-3039. DOI : 10.1109/JSEN.2019.2957108.

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

A. Bloch; E. Bezati; M. Mattavelli 

2019-06-08. Computational Science – ICCS 2019. p. 717-724. DOI : 10.1007/978-3-030-22750-0_70.

A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System

M. Besirli; K. Ture; C. Dehollain; D. Barrettino; M. Mattavelli 

2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 261-264.

An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms

E. Bezati; S. Casale-Brunet; R. Mosqueron; M. Mattavelli 

2019-01-01. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1537-1541. DOI : 10.1109/ICASSP.2019.8682525.

Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements

R. M. Dos Santos; C. Dehollain; M. Mattavelli; D. Barrettino; J-M. Sallese 

2019-01-01. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100-103.

Toward a Dynamic Threshold for Quality-Score Distortion in Reference-Based Alignment

A. A. Hernandez-Lopez; C. Alberti; M. Mattavelli 

2019. 15th International Symposium on Bioinformatics Research and Applications (ISBRA), Barcelona, Spain, June 3–6, 2019.

Execution Trace Graph of Dataflow Process Networks

S. Casale-Brunet; M. Mattavelli 

Ieee Transactions On Multi-Scale Computing Systems. 2018-07-01. Vol. 4, num. 3, p. 340-354. DOI : 10.1109/TMSCS.2018.2790921.

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

A. Modas; S. Casale-Brunet; R. Stewart; E. Bezati; J. Ahmad et al. 

2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263-268.

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

A. Prihozhy; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337-342.

High Precision Capacitive Moisture Sensor for Polymers

R. M. Dos Santos; J-M. Sallese; M. Mattavelli; C. Dehollain; D. Barrettino 

2018-01-01. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212-215.

High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow Programs

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli 

IEEE Transactions on Multi-Scale Computing Systems. 2018. Vol. 4, num. 2, p. 127-140. DOI : 10.1109/TMSCS.2017.2774294.

Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS)

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

M. Michalska; J. J. Ahmad; E. Bezati; S. Casale-Brunet; M. Mattavelli 

2017-09-21.  p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

M. Michalska; E. Bezati; S. Casale-Brunet; M. Mattavelli 

2017-08-28.  p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.

High level synthesis of Smith-Waterman dataflow implementations

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2017-03-05.  p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.

MPEG-G the emerging standard for genomic data compression

M. Hernaez; C. Alberti; M. Mattavelli; I. Ochoa 

2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.

Differential gene expression with lossy compression of quality scores in RNA-seq data

A. A. Hernandez-Lopez; J. Voges; C. Alberti; M. Mattavelli; J. Ostermann 

2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.

Trace-based manycore partitioning of stream-processing applications

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. Janneck 

2016-11-06.  p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.

High-level system synthesis and optimization of dataflow programs for MPSoCs

E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck 

2016-11-06.  p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

M. Michalska; N. Zufferey; E. Bezati; M. Mattavelli 

2016-09-21.  p. 217-224. DOI : 10.1109/MCSoC.2016.25.

Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2016-09-21.  p. 289-296. DOI : 10.1109/MCSoC.2016.39.

High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2016-09-21.  p. 101-108. DOI : 10.1109/MCSoC.2016.23.

Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAs

E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck 

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. Vol. 36, num. 4, p. 699-703. DOI : 10.1109/TCAD.2016.2597215.

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck 

2016-07-17.  p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.

On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling

K. Jerbi; H. Yviquel; A. Sanchez; D. Renzi; D. J. De Saint Jorre et al. 

Journal of Signal Processing Systems. 2016-03-05. Vol. 87, num. 1, p. 127-138. DOI : 10.1007/s11265-016-1113-x.

Comparison of high-throughput sequencing data compression tools

I. Numanagic; J. K. Bonfield; F. Hach; J. Voges; J. Ostermann et al. 

Nature Methods. 2016. Vol. 13, p. 1005-1008. DOI : 10.1038/nmeth.4037.

An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values

C. Alberti; N. Daniels; M. Hernaez; J. Voges; R. L. Goldfeder et al. 

2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA, DOI : 10.1109/Dcc.2016.39.

Performance Estimation Based Multicriteria Partitioning Approach for Dynamic Dataflow Programs

M. Michalska; N. Zufferey; M. Mattavelli 

Journal of Electrical and Computer Engineering. 2016-01-01.  p. 8536432. DOI : 10.1155/2016/8536432.

Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery Strategies

C. Massimo; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck 

Journal of Signal Processing Systems. 2015.  p. 1-11. DOI : 10.1007/s11265-015-1083-4.

Automated Design Flow for Multi-Functional Dataflow-Based Platforms

C. Sau; P. Meloni; L. Raffo; F. Palumbo; E. Bezati et al. 

Journal of Signal Processing Systems -Signal Image and Video Technology-. 2015.  p. 1-23. DOI : 10.1007/s11265-015-1026-0.

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

M. Michalska; J. Boutellier; M. Mattavelli 

2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.

Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.

Synthesis and Optimization of Pipelines for HW Implementations of Dataflow Programs

A. Prihozhy; E. Bezati; A. A-H. Ab Rahman; M. Mattavelli 

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015.  p. 1-1. DOI : 10.1109/TCAD.2015.2427278.

Actor Merging for Dataflow Process Networks

J. Boutellier; J. Ersfolk; J. Lilius; M. Mattavelli; G. Roquier et al. 

Ieee Transactions On Signal Processing. 2015. Vol. 63, num. 10, p. 2496-2508. DOI : 10.1109/Tsp.2015.2411229.

TURNUS: an open-source design space exploration framework for dynamic stream programs

S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. 

2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling

M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck 

2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.

MPEG high efficient video coding stream programming and many-cores scalability

D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. 

2014. 

TURNUS: An open-source design space exploration framework for dynamic stream programs

S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. 

2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.

Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control

S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck 

2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.

Coarse grain clock gating of streaming applications in programmable logic implementations

E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May – 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.

Characterizing communication behavior of dataflow programs using trace analysis

J. W. Janneck; S. Casale-Brunet; M. Mattavelli 

2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.

Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms

D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet 

2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling

M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck 

2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. 

2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck 

2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.

A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

A. A-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli 

2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.

ECMA-407: A New 3D audio codec implementation up to NHK 22.2

J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. 

2014. The 28th VDT International Convention 2014.

ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL

J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. 

2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

E. Bezati; R. Thavot; G. Roquier; M. Mattavelli 

Journal Of Real-Time Image Processing. 2014. Vol. 9, num. 1, p. 251-262. DOI : 10.1007/s11554-013-0326-5.

Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.

Methods to explore design space for MPEG RMC codec specifications

S. Casale-Brunet; A. Elguindy; E. Bezati; R. Thavot; G. Roquier et al. 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1278-1294. DOI : 10.1016/j.image.2013.08.012.

Reconfigurable media coding: An overview

E. S. Jang; M. Mattavelli; M. Preda; M. Raulet; H. Sun 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1215-1223. DOI : 10.1016/j.image.2013.08.008.

Modeling Control Tokens for Composition of CAL Actors

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli 

2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS

J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius 

2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624.

Systems Design Space Exploration by Serial Dataflow Program Executions

S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.

Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study

A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli 

2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

Porting an MPEG-HEVC decoder to a low-power many-core platform

D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

E. Bezati; M. Mattavelli; J. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.

Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework

S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

TURNUS: A design exploration framework for dataflow system design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.

Synthesis and optimization of high-level stream programs

E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck 

2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.

Buffer optimization based on critical path analysis of a dataflow program design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.

Live demonstration: High level software and hardware synthesis of dataflow programs

E. Bezati; G. Roquier; M. Mattavelli 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.

Secure Computing with the MPEG RVC Framework

J. J. Ahmad; S. Li; R. Thavot; M. Mattavelli 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1315-1334. DOI : 10.1016/j.image.2013.08.015.

Performance Benchmarking of RVC based Multimedia Specifications

J. J. Ahmad; S. Li; M. Mattavelli 

2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.

TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.

Representing Guard Dependencies in Dataflow Execution Traces

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.

Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.

Scheduling of dynamic dataflow programs based on state space analysis

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli 

2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.

Profiling of Dataflow Programs Using Post Mortem Causation Traces

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

A. Rahman; A. A. H. Bin; R. Thavot; S. Casale Brunet; E. Bezati et al. 

2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.

Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

G. Roquier; E. Bezati; M. Mattavelli 

Journal of Electrical and Computer Engineering, Special issue on “ESL Design Methodology”. 2012.  p. 2. DOI : 10.1155/2012/484962.

Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs

G. Roquier; E. Benzati; M. Mattavelli; J. W. Janneck 

2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.

Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework

J. J. Ahmad; S. Li; I. Amer; M. Mattavelli 

2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.

Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms

G. Roquier; E. Bezati; R. Thavot; M. Mattavelli 

2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.

A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems

E. Bezati; H. Yviquel; M. Raulet; M. Mattavelli 

2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.

Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs

C. Lucarz; M. Mattavelli; J. Janneck 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.

Scheduling of Dynamic Dataflow Programs with Model Checking

J. Ersfolk; G. Roquier; F. Jokhio; J. Lilius; M. Mattavelli 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.

Methodology for the Hardware/Software Co-Design of Dataflow Programs

G. Roquier; R. Thavot; M. Mattavelli 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.

MPEG Reconfigurable Video Representation

M. Mattavelli 

The MPEG Representation of Digital Media; Springer, 2011.

Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

A. Rahman; A. A. H. Bin; H. Amer; A. Prihozhy; C. Lucarz et al. 

2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.

Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

H. Amer; A. Rahman; A. A. H. Bin; I. Amer; C. Lucarz et al. 

2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011.

Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CAL

A. Rahman; A. A. H. Bin; A. Prihozhy; M. Mattavelli 

Eurasip Journal on Image and Video Processing. 2011. Vol. 2011, num. 19. DOI : 10.1186/1687-5281-2011-19.

Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video Coding

J. Boutellier; C. Lucarz; S. Lafond; V. M. Gomez; M. Mattavelli 

Journal of Signal Processing Systems. 2011. Vol. 63, num. 2, p. 191-202. DOI : 10.1007/s11265-009-0389-5.

Automatic mutli-connectivity interface generation for system designs based on a dataflow description

R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli 

2010.

Hardware and software synthesis of image filters from CAL dataflow specification

A. Rahman; A. Al-Hadi; R. Thavot; M. Mattavelli; P. Faure 

2010.

Generation of Hardware/Software Systems Based on CAL Dataflow Description

R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli 

Algorithm-Architecture Matching for Signal and Image Processing; http://www.springer.com/engineering/signals/book/978-90-481-9964-8?changeHeader: Springer, 2010. p. 275-292.

Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification

A. Rahman; A. A. H. Bin; R. Thavot; M. Mattavelli; P. Faure 

2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.

Automatic mutli-connectivity interface generation for system designs based on a dataflow description

R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli 

2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

C. Lucarz; G. Roquier; M. Mattavelli 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

E. Bezati; M. Mattavelli; M. Raulet 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.

RVC: a Multi-Decoder CAL Composer tool

F. Palumbo; D. Pani; E. Manca; L. Raffo; M. Mattavelli et al. 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.

Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards

J. W. Jannek; M. Mattavelli; M. Raulet; M. Wipliez 

2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010.

The reconfigurable video coding standard

M. Mattavelli; I. Amer; M. Raulet 

IEEE Signal Processing Magazine. 2010. Vol. 27, num. 3, p. 157-167. DOI : 10.1109/MSP.2010.936032.

MPEG Reconfigurable Video Coding

M. Mattavelli; J. W. Janneck; M. Raulet 

Handbook of Signal Processing Systems; Springer, 2010. p. 43-67.

An adaptive system for real-time scalable video streaming with end- to-end qos control

B. Shao; D. Renzi; P. Amon; G. Xilouris; N. Zotos et al. 

2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 – 14, 2010.

Reconfigurable Video coding on Multicore An overview of its main objectives

I. Amer; C. Lucarz; G. Roquier; M. Mattavelli; M. Raulet et al. 

Ieee Signal Processing Magazine. 2009. Vol. 26, p. 113-123. DOI : 10.1109/MSP.2009.934107.

Guest Editorial: Special Issue on Reconfigurable Guest Editorial: Special Issue on Reconfigurable Video Coding

M. Raulet; M. Mattavelli; J. Janneck 

Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0418-4.

A Computationally Efficient Method for Polyphonic Pitch Estimation

R. Zhou; J. D. Reiss; M. Mattavelli; G. Zoia 

EURASIP Journal on Advances in Signal Processing. 2009. Vol. 2009. DOI : 10.1155/2009/729494.

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli 

2009. DASIP, Sophia Antipolis, September 22-24, 2009.

Algorithm/Architecture Co-Exploration of Visual Computing: Overview and Future Perspectives

G. G. (. Lee; Y-K. Chen; M. Mattavelli; E. S. Jang 

IEEE Transactions On Circuits And Systems For Video Technology. 2009. Vol. 19, num. 11, p. 1576-1587. DOI : 10.1109/TCSVT.2009.2031376.

Special Issue: Algorithm/Architecture Co-Exploration of Visual Computing on Emerging Platforms

Y-K. Chen; G. G. (. Lee; M. Mattavelli; E. S. Jang 

IEEE Transactions on Circuits and Systems for Video Technology. 2009. Vol. 19, num. 11, p. 1573-1575. DOI : 10.1109/TCSVT.2009.2034438.

Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework

J. Boutellier; V. Martin Gomez; O. Silven; C. Lucarz; M. Mattavelli 

2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 – 24, 2009.

Motion estimation accelerator with user search strategy for the RVC framework

J. Dubois; M. Mattavelli; J. Miteran; C. Lucarz; R. Mosqueron 

2009. IEEE International Conference on Image Processing, Cairo, Egypt, November 7-10, 2009.

CAL Dataflow Components For an MPEG RVC AVC Baseline Encoder

H. Aman-Allah; K. Maarouf; E. Hanna; I. Amer; M. Mattavelli 

Journal Of Signal Processing Systems For Signal Image And Video Technology. 2009. Vol. 63, p. 227-239. DOI : 10.1007/s11265-009-0399-3.

Automatic synthesis of parsers and validation of bitstreams within the MPEG Reconfigurable Video Coding Framework

C. Lucarz; J. Piat; M. Mattavelli 

Journal of Signal Processing Systems. 2009. DOI : 10.1007/s11265-009-0395-7.

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

G. Roquier; C. Lucarz; M. Mattavelli; M. Wipliez; M. Raulet et al. 

2009. ISCAS 2009, Taipei, Taiwan, May, 2009. p. 799-799.

Reconfigurable Video Coding : Objectives and Technologies

C. Lucarz; I. Amer; M. Mattavelli 

2009. IEEE International Conference on Image Processing, Cairo, Egypt: 2009, Cairo, Egypt, 7-10 November, 2009. p. 749-752.

Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple ProfileDecoder Case Study

J. W. Janneck; I. D. Miller; D. B. Parlour; M. Mattavelli; C. Lucarz et al. 

Design, Automation and Test in Europe (DATE08), Munich, Germany,

Video Decoder Reconfigurations and AVS Extensions in the New MPEG Reconfigurable Video Coding Framework

D. Ding; L. Yu; C. Lucarz; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework

J. Boutellier; V. Sadhanala; C. Lucarz; P. Brisk; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems. SiPS 2008. , Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework

M. Raulet; J. Piat; C. Lucarz; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

OpenDF – A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

S. Bhattacharyya; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. 

2008. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.

Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case Study

J. W. Janneck; I. D. Miller; D. B. Parlour; M. Mattavelli; C. Lucarz et al. 

2008. Design, Automation and Test in Europe (DATE), Munich, Germany, 2008.

A co-design platform for Algorithm/Architecture design exploration

C. Lucarz; M. Mattavelli; J. Dubois 

2008. IEEE International Conference on Multimedia & Expo, Hannover, Germany, June 23-26, 2008.

A Multimedia Terminal for Adaptation and End-to-end QoS Control

B. Shao; M. Mattavelli; D. Renzi; M. Andrade; S. Battista et al. 

2008. IEEE International Conference on Multimedia & Expo (ICME 2008), Hannover, Germany, June 23-26, 2008.

How to Make Stream Processing More Mainstream

B. Shuvra; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. 

2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.

Music Onset Detection Based on Resonator Time Frequency Image

M. Mattavelli; G. Zoia; R. Zhou 

IEEE Transactions On Audio, Speech And Language Processing. 2008. Vol. 16, num. 8, p. 1685-1695. DOI : 10.1109/TASL.2008.2002042.

OpenDF – A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

M. Mattavelli; S. S. Bhattacharyya; J. Eker; C. von Platen; G. Brebner et al. 

ACM SIGARCH Computer Architecture News, Special Issue: MCC08 – Multicore Computing 2008. 2008. Vol. 36, num. 5, p. 29-35.

Dataflow/Actor-Oriented language for the design of complex signal processing systems

C. Lucarz; M. Mattavelli; M. Wipliez; G. Roquier; M. Raulet et al. 

2008. Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, Bruxelles, Belgium, 24-26 November 2008. p. 168-175.

Efficient Data Flow Variable Length Decoding Implementation for the MPEG Reconfigurable Video Coding Framework

J. Li; D. Ding; C. Lucarz; S. Keller; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework

J. Boutellier; V. Sadhanala; C. Lucarz; P. Brisk; M. Marco Mattavelli 

2008. Signal Processing Systems, 2008. SiPS 2008. IEEE Workshop on, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 182-187.

Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework

M. Raulet; J. Piat; C. Lucarz; M. Mattavelli 

2008. 2008 IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008. p. 1520-6130.

Dataflow design of a co-processor architecture for image processing

R. Thavot; R. Mosqueron; M. Alisafaee; C. Lucarz; M. Mattavelli et al. 

2008. Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008.

Smart camera based on embedded HW/SW coprocessor

R. Mosqueron; J. Dubois; M. Mattavelli; D. Mauvilet 

Journal on Embedded Systems, EURASIP. 2008. Vol. 2008.

A Multimedia Terminal for Adaptation and End-to-end QoS Control

B. Shao; M. Mattavelli; D. Renzi; M. Andrade; S. Battista et al. 

2008. Proceedings of the IEEE International Conference on Multimedia & Expo (ICME 2008)., Hannover, Germany, 2008.

A Multimedia Terminal Supporting Adaptation for QoS Control

B. Shao; D. Renzi; M. Mattavelli; S. Battista; S. Keller 

2008. 9th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS 2008), Klagenfurt, Austria, May 7-9, 2008.

Multimedia Terminal Architecture: An Inter-Operable Approach

B. Shao; M. Mattavelli; M. Andrade; S. Keller; G. Ciobanu et al. 

2008. The First ACS/IEEE International Workshop on Wireless Internet Services (WISe’08) in conjunction with The Sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, April 1-4 2008.

[ISO/IEC MPEG contribution] Function Units for Conversion from Syntax to Sequence of Tokens: BTYPE

D. Ding; C. Lucarz; M. Mattavelli; L. Yu 

2008

[ISO/IEC MPEG contribution] Functional Units for RVC Toolbox: Variable Length Decoding

C. Lucarz; J. Li; M. Mattavelli; D. Ding 

2008

[ISO/IEC MPEG contribution] Auto-generation of RVC Parser from BSDL Syntax Description: Variable Length Decoding

C. Lucarz; J. Li; M. Mattavelli; D. Ding 

2008

[ISO/IEC MPEG contribution] BSDL Description of MPEG-4 SP and AVC BP Bitstream Syntax for RVC Framework

C. Lucarz; D. Ding; J. Li; M. Mattavelli 

2008

[ISO/IEC MPEG contribution] Update of Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework

D. Ding; M. Mattavelli; C. Lucarz; L. Yu 

2008

Smart camera with embedded co-processor: a postal sorting application

R. Mosqueron; J. Dubois; M. Mattavelli 

2008. Optical and Digital Image Processing , Strasbourg, France , April 7 2008.

A new time-frequency representation for music signal analysis: Resonator Time-Frequency Image

R. Zhou; M. Mattavelli 

2007. 9th International Symposium on Signal Processing and its Applications, Sharjah, U ARAB EMIRATES, Feb 12-15, 2007. p. 1278-1281.

A Simplified 8 × 8 Transformation And Quantization Real-Time Ip-Block For MPEG-4 H.264/AVC Applications: A New Design Flow Approach

I. Amer; W. Badawy; G. Jullien; M. Mattavelli; R. Turney 

Journal of Circuits, Systems, and Computers. 2007. Vol. 16, num. 6, p. 1011-1026. DOI : 10.1142/S021812660700399X.

Reconfigurable Media Coding: Self-Describing Multimedia Bitstreams

J. Thomas-Kerr; J. Janneck; M. Mattavelli; I. Burnett; C. Ritz 

2007. SIPS 2007, Shanghai, Oct. 17-19 2007.

[ISO/IEC MPEG contribution] Implement flexible FUs according to the processing mechanism in CVC WD using CAL (Results of Core Experiment 1.1) and analysis of the compactness of RVC Abstract Decoder Model (Results of Core Experiment 1.3)

C. Lucarz; J. Thomas-Kerr; M. Mattavelli; J. Janneck; D. Parlour et al. 

2007

High Performance Embedded Co-Processor Architecture For CMOS Imaging Systems

R. Mosqueron; J. Dubois; M. Mattavelli 

2007. Workshop on Design and Architectures for Signal and Image Processing, Grenoble (France), November 2007.

A HW/SW codesign platform for Algorithm-Architecture mapping

C. Lucarz; M. Mattavelli; J. Dubois 

2007. Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 27-29.

[ISO/IEC MPEG contribution] Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework

D. Ding; M. Mattavelli; C. Lucarz; L. Yu 

2007

[ISO/IEC MPEG contribution] A systematic procedure for the generation of a CAL parser from BDSL in the RVC framework – result CE 1.1

C. Lucarz; J. Thomas-Kerr; M. Mattavelli 

2007

[ISO/IEC MPEG contribution] Serialized version of some MPEG-4 SP FUs

C. Lucarz; M. Mattavelli; D. Parlour 

2007

[ISO/IEC MPEG contribution] Reconfigurability potential of the MPEG-4 SP decoder (results of CE 1.1)

C. Lucarz; J. Thomas-Kerr; M. Mattavelli 

2007

[ISO/IEC MPEG contribution] Implementation of multiple reference frame support in RVC CAL model

C. Lucarz; M. Mattavelli 

2007

[ISO/IEC MPEG contribution] Compression of the RVC DDL Decoder Description with BiM (results of Core Experiment 1.3 in RVC)

C. Lucarz; M. Mattavelli 

2007

[ISO/IEC MPEG contribution] RVC Functional Units naming process proposal

C. Lucarz; M. Mattavelli; A. Kinane; S. Lee; S. Lee 

2007

[ISO/IEC MPEG contribution] Update of the Textual specification of Functional Units, DDL and FUs SW of the MPEG-4 SP RVC Abstract Decoder Model (Results of CE 2.1)

M. Mattavelli; C. Lucarz; A. Kinane; K. Radha; J. Janneck et al. 

2007

[ISO/IEC MPEG contribution] A proposal for the classification and mapping of MPEG video coding technology into Functional Units for the RVC framework (Results of CE 2.2)

C. Lucarz; M. Mattavelli; A. Kinane; R. Krisha 

2007

A platform for mixed HW/SW algorithm specifications for the exploration of SW and HW partitioning

C. Lucarz; M. Mattavelli 

2007. PATMOS, Göteborg, Sweden, September 3-5, 2007. p. 485-494. DOI : 10.1007/978-3-540-74442-9_47.

Reconfigurable media coding: a new specification model for multimedia coders

C. Lucarz; M. Mattavelli; J. Thomas-Kerr; J. Janneck 

2007. SiPS, Shanghai, China, October 17-19, 2007.

SMIL to MPEG-4 BIFS Conversion

B. Shao; L. Velazquez; N. Scaringella; N. Singh; M. Mattavelli 

2006. The Second International Conference on Automated Production of Cross Media Content for Multi-Channel Distribution (AXMEDIS’06), Leeds, UK, December 13-15, 2006. p. 77-84. DOI : 10.1109/AXMEDIS.2006.49.

[ISO/IEC MPEG contribution] Report on results of RVC CE 2.1 Reshape the current MPEG-4 SP CAL decoder according to the current FU interface in RVC WM

M. Mattavelli; A. Kinane; C. Lucarz; J. Janneck; D. Parlour 

2006

[ISO/IEC MPEG contribution] Report on results of RVC CE 2.2: Explore the extensibility of FUs

C. Lucarz; M. Mattavelli; A. Kinane 

2006

Configurable motion-estimation hardware accelerator module for the MPEG-4 reference hardware description platform

J. Dubois; M. Mattavelli; L. Pierrefeu; J. Miteran 

2005. IEEE International Conference on Image Processing, ICIP 2005, Genova, September 11-14, 2005. p. 591-594.

A Virtual Socket Framework for Rapid Emulation of Video and Multimedia Designs

P. Schumacher; M. Mattavelli; A. Chirila-Rus; R. Turney 

2005. ICME 2005, Amsterdam, July 6-8, 2005. p. 872-875.

A Software/Hardware Platform For Rapid Prototyping of Video and Multimedia Designs

P. Schumacher; M. Mattavelli; A. Chirila-Rus; R. Turney 

2005. IWSOC 2005, Banff, July 20-24, 2005. p. 30-33. DOI : 10.1109/IWSOC.2005.27.

High Level Extraction of SoC Architectural Information from Generic C Algorithmic Descriptions

M. Ravasi; M. Mattavelli 

2005. IWSOC, Banff, July 20-24, 2005.

High-abstraction level complexity analysis and memory architecture simulations of multimedia algorithms

M. Ravasi; M. Mattavelli 

2005. JFAAA’2005, Dijon, January 18-21, 2005. p. 673-684.

Efficient error correction solutions for OFDM-based wireless video

M. Lattuada; R. Posega; M. Mattavelli; D. Mlynek 

2005. IEEE, PRIME 2005 Conference, Ph.D. Research In Micro-Electronics & Electronics, Lausanne, July 25-28, 2005. p. 205-208.

An automatic tool for high-level algorithmic complexity evaluation and optimization for system design

M. RAVASI; C. CLERC; M. MATTAVELLI; D. MLYNEK 

2004. Symposium on Design, Test, Integration and Packaging of MWMS/MOEMS, Montreux , SUISSE, May 12, 2004.

Data Dependences Critical Path Evaluation at C/C++ System Level

A. Prihozhy; M. Mattavelli; D. Mlynek 

2003.  p. 569-5792003.

High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder

M. Ravassi; M. Mattavelli; P. Schumacher; R. Turney 

2003. 

Embedded co-processor architecture for CMOS based image acquisition

J. Dubois; M. Mattavelli 

2003. International Conference on Image Processing, ICIP 2003, Barcelona, September 14-17, 2005. p. 591-594.

Embedded Co-Processor Architecture for CMOS Based Image Acquisition

J. Dubois; M. Mattavelli 

2003.  p. 591-594.

Improving Dvb-T Forward Error Correction By Concatenated Turbo Code Scheme

M. Lattuada; R. Posega; M. Mattavelli; D. Mlynek 

2003. 

High-Level Algorithmic Complexity Analysis for the Implementation of a Motion-JPEG2000 Encoder

M. Ravasi; M. Mattavelli; P. Schumacher; R. Turney 

2003.  p. 440-450.

Lossy compression of TPC data and trajectory tracking efficiency for the ALICE experiment

A. Nicolaucig; M. Ivanov; M. Mattavelli 

Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 2003. Vol. 500, num. -2, p. 412-420. DOI : 10.1016/S0168-9002(03)00343-7.

High-level algorithmic complexity evaluation for system design

M. Ravasi; M. Mattavelli 

Journal of Systems Architecture. 2003. Vol. 48, num. 13-15, p. 403-427. DOI : 10.1016/S1383-7621(03)00038-9.

Techniques for Optimization of Net Algorithms

A. Prihozhy; D. Mlynek; M. Solomennik; M. Mattavelli 

2002. International Conference on Parallel Computing in Electrical Engineering, PARALEC’02, Warsaw, September 22-25, 2002. p. 211-216.

An interpreted approach to multimedia streams protection

C. Alberti; A. Romeo; M. Mattavelli; D. Mlynek 

2002. Eusipco 2002, Toulouse, September 2002. p. 63-66.

A Scalable And Programmable Architecture For 2-D DWT Decoding

M. Ravasi; L. Tenze; M. Mattavelli 

IEEE Transactions on Circuits and Systems for Video Technology. 2002. Vol. 12, num. 8, p. 671-677. DOI : 10.1109/TCSVT.2002.800863.

The MIN PFS problem and piecewise linear model estimation

E. Amaldi; M. Mattavelli 

Discrete Applied Mathematics. 2002. Vol. 118, num. 1-2, p. 115-143. DOI : 10.1016/S0166-218X(01)00260-8.

Compression of TPC data in the ALICE experiment

A. Nicolaucig; M. Mattavelli 

Nuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 2002. Vol. 487, num. 3, p. 542-556. DOI : 10.1016/S0168-9002(01)02195-7.

Fast Line Detection Algorithms Based on Combinatorial Optimization

M. Mattavelli; V. Noel; E. Amaldi 

2001.  p. 410-419.

A System-on-a-chip for Multimedia Stream Processing and Communication

E. Juarez; M. Mattavelli; D. Mlynek 

2000. 

A System-on-a-chip for MPEG-4 Multimedia Stream Processing and Communication

E. Juarez; M. Mattavelli; D. Mlynek 

2000. 

Scheduling Strategies for 2D Wavelet Coding Implementations

M. Ravasi; M. Mattavelli; D. Mlynek 

2000. 

A System-on-a-chip for Multimedia Stream Processing & Communication

E. Juarez; M. Mattavelli; D. Mlynek 

2000. 

A VLSI Architecture for MPEG-4 Stream Processing and Communication

E. Juarez; M. Mattavelli; D. Mlynek 

2000. 

A Hardware Oriented Analysis of Cryptographic Systems for Multimedia Applications

A. Romeo; M. Mattavelli 

2000. 

An Efficient Host/Co-Processor Solution For Mpeg-4 Audio Composition

L. Le Bourhis; G. Zoia; M. Mattavelli; D. Mlynek 

IEEE Transactions on Consumer Electronics. 1999. Vol. 45, num. 4, p. 1290-1300. DOI : 10.1109/30.809221.

An efficient Host/Co-Processor Solution for MPEG-4 Audio Composition

L. Le Bourhis; G. Zoia; M. Mattavelli; D. Mlynek 

1999.  p. 26-27.

Very high throughput Crypto-System Architectures: The RPK Solution

A. Romeo; G. Romolotti; M. Mattavelli; D. Mlynek 

1999. International Conference on Consumer Electronics, Los Angeles, June 22-24, 1999. p. 96-97.

Wavelet Image Compression for mobile/portable Application

M. Ravasi; M. Mattavelli; D. Mlynek; A. Buttar; S. Sondagar 

1999. International Conference on Consumer Electronics, Los Angeles, June 22-24, 1999. p. 374-375.

Cryptosystem architectures for very high throughput multimedia encryption

A. Romeo; G. Romolotti; M. Mattavelli; D. Mlynek 

1999. September 5-8, 1999. p. 261-264.

An efficient line detection algorithm based on a new combinatorial optimization formulation

M. Mattavelli; V. Noel; E. Amaldi 

1998. 

Vector Tracing Techniques for Motion Estimation Algorithms in Video Coding

M. Mattavelli; G. Zoia 

1998.  p. 2097-2100.

An Efficient Motion Estimation Algorithm Based on Tracing Techniques on Large Search Windows

M. Mattavelli; G. Zoia 

1998. 

A Parallel Multimedia Processor for Macroblok Based Compression Standars

M. Mattavelli; S. Brunetton; D. Mlynek 

1997.  p. 570-573.

Computational Graceful Degradation for Video Sequence Ddecoding

M. Mattavelli; S. Brunetton; D. Mlynek 

1997. 

Motion analysis and estimation

M. Mattavelli / M. Kunt (Dir.)  

Lausanne, EPFL, 1997. 

Estimating piecewise linear models using combinatorial optimization techniques

M. Mattavelli; E. Amaldi 

1996.  p. 815-818.

Image Restoration by 1-D Kalman filtering on oriented image decompositions

M. Mattavelli; G. Thonet; V. Vaerman; B. Macq 

1996.  p. 2771-2774.

Remote teaching by multimedia communications: the BETEL project

A. Basso; M. Mattavelli; Y. Pustzaszeri; J. Hubaux 

1995