LTS5 research in ultrasound imaging
Regularization methods in ultrasound imaging
In terms of acoustic wave propagation, ultrasound imaging poses an inverse problem which relates the tissue reflectivity (image under scrutiny) to the backscattered echoes (the measurements). Standard imaging methods are based on a well-known algorithm called Delay-and-sum (DAS). The major advantage of DAS is that it is fast and highly parallelizable. Its main drawback is that it is an inaccurate solution of the inverse problem which leads to low-quality images. One research topic in LTS5 consists in exploring alternatives to DAS mainly based on regularization approaches. The idea is to inject prior knowledge (sparsity of the image in a well-chosen model) about the tissue reflectivity in order to leverage the ill-posedness of the problem. The problem is recast as a convex optimization algorithm and solved using standard algorithms such as ADMM, primal-dual forward backward or FISTA.
Figure: Cyst image reconstructed with the DAS algorithm (left) and with the sparse regularization approach (right).
Compressed sensing and deep learning in ultrasound imaging
Compressed sensing or compressive sensing (CS) is a well-known mathematical framework which ensures perfect recovery of compressible signals from random projections with fewer samples than Nyquist rate. The recovery is achieved by solving a convex optimization problem where the most compressible solution which fits to the measurements is identified. This framework has been substantially studied in the last ten years and has lead to great successes such as: the Rice single pixel camera or the Sparse MRI. At LTS5, we are currently working on applying the CS framework to ultrasound imaging. The first idea is to exploit the intrinsic structure of US data which can be modelled as a stream of pulses, compressible in a redundant dictionary made of shifted replica of the ultrasound pulse. The second idea consists in designing acquisition schemes that are most suited to the CS framework. The last work focuses on designing efficient reconstruction algorithms. To do so, we are intensively working on deep learning algorithms which are becoming extremely popular nowadays due to their ability to perform a various of tasks (object recognition, classification, text generation, image colorization etc.). At LTS5, we are currently focusing on three main deep neural netwrok architectures for ultrasound imaging:
- DNN that maps convex optimization algorithms such as Fast-Iterative thredsholding algorithm (FISTA);
- Fully connected architectures (Stacked denoising autoencoders, Multi-layer perceptron);
- Convolutional neural networks.
Toward a common standard for data and specimen provenance in life sciencesLearning Health Systems. 2023-04-18. p. e10365. DOI : 10.1002/lrh2.10365.
FM -Directories: Extending the Burrows-Wheeler Transform for String Labeled Vertex Graphs of (Almost) Arbitrary Topology2023-01-01. Data Compression Conference (DCC), Snowbird, UT, Mar 21-24, 2023. p. 355-355. DOI : 10.1109/DCC55655.2023.00087.
Integrated Electronics for Deep Implants to Remotely Monitor HemodynamicsLausanne, EPFL, 2023.
The impact of NFT profile pictures within social network communities2022-09-30. GoodIT 2022: ACM International Conference on Information Technology for Social Good, Limassol, Cyprus, September 7 – 9, 2022. p. 283-291. DOI : 10.1145/3524458.3547230.
Dynamic SIMD Parallel Execution on GPU from High-Level Dataflow SynthesisJournal Of Low Power Electronics And Applications. 2022-09-01. Vol. 12, num. 3, p. 40. DOI : 10.3390/jlpea12030040.
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network ExecutionJournal Of Low Power Electronics And Applications. 2022-09-01. Vol. 12, num. 3, p. 36. DOI : 10.3390/jlpea12030036.
SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis2022-02-04. 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 20-23, 2021. p. 62-68. DOI : 10.1109/MCSoC51149.2021.00017.
Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms2022-02-04. 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC), Singapore, December 20-23, 2021. p. 69-76. DOI : 10.1109/MCSoC51149.2021.00018.
An Implantable Inductive Sensor for Direct and Continuous Monitoring of the Pulmonary Artery Cross-Sectional Area2022. 2022 IEEE Biomedical Circuits and Systems Conference (BioCAS), Taipei, Taiwan, October 13-15, 2022. p. 31-35. DOI : 10.1109/BioCAS54905.2022.9948566.
A Capacitively-Coupled Chopper Instrumentation Amplifier for Implantable Bridge Sensor Systems2022-01-01. 20th IEEE Interregional NEWCAS Conference (IEEE NEWCAS), Quebec City, CANADA, Jun 19-22, 2022. p. 208-212. DOI : 10.1109/NEWCAS52662.2022.9842137.
MPEG-G Reference-Based Compression of Unaligned Reads Through Ultra-Fast Alignments2022-01-01. Data Compression Conference (DCC), Snowbird, UT, Mar 22-25, 2022. p. 478-478. DOI : 10.1109/DCC52660.2022.00089.
Inter-actions parallel execution on GPU from high-level dataflow synthesis2022. 2021 55th Asilomar Conference on Signals, Systems, and Computers (ACSSC 2021), Pacific Grove, CA, USA, 31 Oct.-3 Nov. 2021. p. 1151-1155. DOI : 10.1109/IEEECONF53345.2021.9723288.
A 0.4 nJ Excitation Energy Bridge-to-Digital Converter for Implantable Pulmonary Artery Pressure Monitoring2021-10-07. 2021 IEEE Biomedical Circuits and Systems Conference (BioCAS), Berlin, Germany, October 7-9, 2021. DOI : 10.1109/BioCAS49922.2021.9644941.
An Introduction to MPEG-G: The First Open ISO/IEC Standard for the Compression and Exchange of Genomic Sequencing DataProceedings Of The Ieee. 2021-09-01. Vol. 109, num. 9, p. 1607-1622. DOI : 10.1109/JPROC.2021.3082027.
Networks of Ethereum Non-Fungible Tokens: A graph-based analysis of the ERC-721 ecosystem2021-01-01. 4th IEEE International Conference on Blockchain (Blockchain), ELECTR NETWORK, Dec 06-08, 2021. p. 188-195. DOI : 10.1109/BLOCKCHAIN53845.2021.00033.
Fully Soft-Switched High Step-Up Nonisolated Three-Port DC-DC Converter Using GaN HEMTsIeee Transactions On Industrial Electronics. 2020-10-01. Vol. 67, num. 10, p. 8371-8380. DOI : 10.1109/TIE.2019.2944068.
Pipeline Synthesis and Optimization from Branched Feedback Dataflow ProgramsJournal Of Signal Processing Systems For Signal Image And Video Technology. 2020-07-11. Vol. 92, p. 1091–1099. DOI : 10.1007/s11265-020-01568-5.
High Precision Capacitive Moisture Sensor for Polymers: Modeling and ExperimentsIEEE Sensors Journal. 2020-03-15. Vol. 20, num. 6, p. 3032-3039. DOI : 10.1109/JSEN.2019.2957108.
CMOS-Based Readout and Control Electronics for Microgrippers2020-01-01. IEEE Sensors Conference, ELECTR NETWORK, Oct 25-28, 2020. DOI : 10.1109/SENSORS47125.2020.9278921.
Programming Heterogeneous CPU-GPU Systems by High-Level Dataflow Synthesis2020. 2020 IEEE Workshop on Signal Processing Systems (SiPS), [Virtual Conference], October 20 – 22, 2020. p. 1-6. DOI : 10.1109/SiPS50750.2020.9195250.
Low-Cost Readout Electronics for Piezoresistive MEMS-Based Transducers2019-01-01. IEEE International Instrumentation and Measurement Technology Conference (I2MTC), Auckland, NEW ZEALAND, May 20-23, 2019. p. 1597-1601. DOI : 10.1109/I2MTC.2019.8826916.
A CMOS Analog Front-End for Implantable Pulmonary Artery Pressure Monitoring System2019-01-01. 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, SWITZERLAND, Jul 15-18, 2019. p. 261-264. DOI : 10.1109/PRIME.2019.8787811.
An Heterogeneous Compiler Of Dataflow Programs For Zynq Platforms2019-01-01. 44th IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Brighton, ENGLAND, May 12-17, 2019. p. 1537-1541. DOI : 10.1109/ICASSP.2019.8682525.
Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements2019-01-01. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100-103. DOI : 10.1109/LAED.2019.8714730.
Execution Trace Graph of Dataflow Process NetworksIeee Transactions On Multi-Scale Computing Systems. 2018-07-01. Vol. 4, num. 3, p. 340-354. DOI : 10.1109/TMSCS.2018.2790921.
Shared-variable Synchronization Approaches for Dynamic Data Flow Programs2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263-268. DOI : 10.1109/SiPS.2018.8598431.
Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337-342. DOI : 10.1109/SiPS.2018.8598386.
High Precision Capacitive Moisture Sensor for Polymers2018-01-01. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212-215. DOI : 10.1109/ICSENS.2018.8589775.
Transcriptome reconstruction with quality score distortion in reference-based alignmentResearch in computational molecular biology (RECOMB), Paris, France, April 19-24, 2018.
High-Precision Performance Estimation for the Design Space Exploration of Dynamic Dataflow ProgramsIEEE Transactions on Multi-Scale Computing Systems. 2018. Vol. 4, num. 2, p. 127-140. DOI : 10.1109/TMSCS.2017.2774294.
Design space exploration of dataflow-based Smith-Waterman FPGA implementations2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.
Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)2017-09-21. p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.
Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms2017-08-28. p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.
High level synthesis of Smith-Waterman dataflow implementations2017-03-05. p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.
MPEG-G the emerging standard for genomic data compression2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.
Trace-based manycore partitioning of stream-processing applications2016-11-06. p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.
High-level system synthesis and optimization of dataflow programs for MPSoCs2016-11-06. p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.
Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures2016-09-21. p. 217-224. DOI : 10.1109/MCSoC.2016.25.
Programming Models and Methods for Heterogeneous Parallel Embedded Systems2016-09-21. p. 289-296. DOI : 10.1109/MCSoC.2016.39.
High-Precision Performance Estimation of Dynamic Dataflow Programs2016-09-21. p. 101-108. DOI : 10.1109/MCSoC.2016.23.
Clock-Gating of Streaming Applications for Energy Efficient Implementations on FPGAsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2016-08-02. Vol. 36, num. 4, p. 699-703. DOI : 10.1109/TCAD.2016.2597215.
High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms2016-07-17. p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.
On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow ModelingJournal of Signal Processing Systems. 2016-03-05. Vol. 87, num. 1, p. 127-138. DOI : 10.1007/s11265-016-1113-x.
Comparison of high-throughput sequencing data compression toolsNature Methods. 2016. Vol. 13, p. 1005-1008. DOI : 10.1038/nmeth.4037.
Dataflow Programs Analysis and Optimization Using Model Predictive Control Techniques. Two Examples of Bounded Buffer Scheduling: Deadlock Avoidance and Deadlock Recovery StrategiesJournal of Signal Processing Systems. 2015. p. 1-11. DOI : 10.1007/s11265-015-1083-4.
Automated Design Flow for Multi-Functional Dataflow-Based PlatformsJournal of Signal Processing Systems -Signal Image and Video Technology-. 2015. p. 1-23. DOI : 10.1007/s11265-015-1026-0.
Synthesis and Optimization of Pipelines for HW Implementations of Dataflow ProgramsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2015. p. 1-1. DOI : 10.1109/TCAD.2015.2427278.
Actor Merging for Dataflow Process NetworksIeee Transactions On Signal Processing. 2015. Vol. 63, num. 10, p. 2496-2508. DOI : 10.1109/Tsp.2015.2411229.
MPEG high efficient video coding stream programming and many-cores scalability2014.
TURNUS: An open-source design space exploration framework for dynamic stream programs2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.
Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.
Characterizing communication behavior of dataflow programs using trace analysis2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.
Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.
Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.
Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.
Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014. DOI : 10.1109/ESLsyn.2014.6850387.
A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014. p. 5003-5007. DOI : 10.1109/ICASSP.2014.6854554.
ECMA-407: A New 3D audio codec implementation up to NHK 22.22014. The 28th VDT International Convention 2014.
ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.
Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63. DOI : 10.1109/QoMEX.2013.6603211.
Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182. DOI : 10.1109/SiPS.2013.6674501.
Methods to explore design space for MPEG RMC codec specificationsSignal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1278-1294. DOI : 10.1016/j.image.2013.08.012.
Reconfigurable media coding: An overviewSignal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1215-1223. DOI : 10.1016/j.image.2013.08.008.
Modeling Control Tokens for Composition of CAL Actors2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 71-78.
Static and quasi-static compositions of stream processing applications from dynamic dataflow programs2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624. DOI : 10.1109/ICASSP.2013.6638130.
Systems Design Space Exploration by Serial Dataflow Program Executions2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1805-1809. DOI : 10.1109/ACSSC.2013.6810613.
Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013. p. 1796-1800. DOI : 10.1109/ACSSC.2013.6810611.
Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013. p. 63-70.
Porting an MPEG-HEVC decoder to a low-power many-core platform2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.
High-Level Synthesis of Dataflow Programs for Signal Processing Systems2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013. p. 750-754. DOI : 10.1109/ISPA.2013.6703837.
Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 341-342.
TURNUS: A design exploration framework for dataflow system design2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.
Synthesis and optimization of high-level stream programs2013. Electronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.
Buffer optimization based on critical path analysis of a dataflow program design2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.
Live demonstration: High level software and hardware synthesis of dataflow programs2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.
TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013. p. 47-54.
Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.
Representing Guard Dependencies in Dataflow Execution Traces2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.
Scheduling of dynamic dataflow programs based on state space analysis2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664. DOI : 10.1109/ICASSP.2012.6288215.
Profiling of Dataflow Programs Using Post Mortem Causation Traces2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.
Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.
Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.
Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130. DOI : 10.1145/2037252.2037275.
Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.
A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.
Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011. p. 43-48. DOI : 10.1109/SiPS.2011.6088947.
Scheduling of Dynamic Dataflow Programs with Model Checking2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011. p. 37-42. DOI : 10.1109/SiPS.2011.6088946.
Methodology for the Hardware/Software Co-Design of Dataflow Programs2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011. p. 174-179. DOI : 10.1109/SiPS.2011.6088970.
MPEG Reconfigurable Video RepresentationThe MPEG Representation of Digital Media; Springer, 2011.
Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.
Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011. p. 186-191. DOI : 10.1109/SiPS.2011.6088972.
Pipeline Synthesis and Optimization of FPGA-based Video Processing Applications with CALEurasip Journal on Image and Video Processing. 2011. Vol. 2011, p. 19. DOI : 10.1186/1687-5281-2011-19.
Guest Editorial: Special Issue on Reconfigurable Guest Editorial: Special Issue on Reconfigurable Video CodingJournal of Signal Processing Systems. 2011. Vol. 63, p. 177–179. DOI : 10.1007/s11265-009-0418-4.
Quasi-Static Scheduling of CAL Actor Networks for Reconfigurable Video CodingJournal of Signal Processing Systems. 2011. Vol. 63, num. 2, p. 191-202. DOI : 10.1007/s11265-009-0389-5.
Automatic mutli-connectivity interface generation for system designs based on a dataflow description2010.
Hardware and software synthesis of image filters from CAL dataflow specification2010.
Generation of Hardware/Software Systems Based on CAL Dataflow DescriptionAlgorithm-Architecture Matching for Signal and Image Processing; Dordrecht: Springer, 2010. p. 275-292.
Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
Automatic mutli-connectivity interface generation for system designs based on a dataflow description2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.
High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.
RVC: a Multi-Decoder CAL Composer tool2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.
Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010. p. 223–234. DOI : 10.1145/1730836.1730864.
The reconfigurable video coding standardIEEE Signal Processing Magazine. 2010. Vol. 27, num. 3, p. 157-167. DOI : 10.1109/MSP.2010.936032.
An adaptive system for real-time scalable video streaming with end- to-end qos control2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 – 14, 2010.
Reconfigurable Video coding on Multicore An overview of its main objectivesIeee Signal Processing Magazine. 2009. Vol. 26, p. 113-123. DOI : 10.1109/MSP.2009.934107.
Hardware synthesis of complex standard interfaces using CAL dataflow descriptions2009. DASIP, Sophia Antipolis, September 22-24, 2009.
Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 – 24, 2009.
Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case StudyDesign, Automation and Test in Europe (DATE08), Munich, Germany,
OpenDF – A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems2008. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.
How to Make Stream Processing More Mainstream2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.
Dataflow/Actor-Oriented language for the design of complex signal processing systems2008. Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, Bruxelles, Belgium, 24-26 November 2008. p. 168-175.
Dataflow design of a co-processor architecture for image processing2008. Conference on Design and Architectures for Signal and Image Processing , DASIP 2008, Bruxelles, Belgium, 24-26 November 2008.
Multimedia Terminal Architecture: An Inter-Operable Approach2008. The First ACS/IEEE International Workshop on Wireless Internet Services (WISe’08) in conjunction with The Sixth ACS/IEEE International Conference on Computer Systems and Applications (AICCSA-08), Doha, Qatar, April 1-4 2008. p. 981-986. DOI : 10.1109/AICCSA.2008.4493664.
[ISO/IEC MPEG contribution] Function Units for Conversion from Syntax to Sequence of Tokens: BTYPE
[ISO/IEC MPEG contribution] Functional Units for RVC Toolbox: Variable Length Decoding
[ISO/IEC MPEG contribution] Auto-generation of RVC Parser from BSDL Syntax Description: Variable Length Decoding
[ISO/IEC MPEG contribution] BSDL Description of MPEG-4 SP and AVC BP Bitstream Syntax for RVC Framework
[ISO/IEC MPEG contribution] Update of Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework
A new time-frequency representation for music signal analysis: Resonator Time-Frequency Image2007. 9th International Symposium on Signal Processing and its Applications, Sharjah, U ARAB EMIRATES, Feb 12-15, 2007. p. 1278-1281. DOI : 10.1109/ISSPA.2007.4555594.
[ISO/IEC MPEG contribution] Implement flexible FUs according to the processing mechanism in CVC WD using CAL (Results of Core Experiment 1.1) and analysis of the compactness of RVC Abstract Decoder Model (Results of Core Experiment 1.3)
High Performance Embedded Co-Processor Architecture For CMOS Imaging Systems2007. Workshop on Design and Architectures for Signal and Image Processing, Grenoble (France), November 2007.
A HW/SW codesign platform for Algorithm-Architecture mapping2007. Workshop on Design and Architectures for Signal and Image Processing (DASIP), Grenoble, France, November 27-29.
[ISO/IEC MPEG contribution] Classification of Tokens for FUs of MPEG-4 SP and MPEG-4/AVC in RVC Framework
[ISO/IEC MPEG contribution] A systematic procedure for the generation of a CAL parser from BDSL in the RVC framework – result CE 1.1
[ISO/IEC MPEG contribution] Serialized version of some MPEG-4 SP FUs
[ISO/IEC MPEG contribution] Reconfigurability potential of the MPEG-4 SP decoder (results of CE 1.1)
[ISO/IEC MPEG contribution] Implementation of multiple reference frame support in RVC CAL model
[ISO/IEC MPEG contribution] Compression of the RVC DDL Decoder Description with BiM (results of Core Experiment 1.3 in RVC)
[ISO/IEC MPEG contribution] RVC Functional Units naming process proposal
[ISO/IEC MPEG contribution] Update of the Textual specification of Functional Units, DDL and FUs SW of the MPEG-4 SP RVC Abstract Decoder Model (Results of CE 2.1)
[ISO/IEC MPEG contribution] A proposal for the classification and mapping of MPEG video coding technology into Functional Units for the RVC framework (Results of CE 2.2)
[ISO/IEC MPEG contribution] Report on results of RVC CE 2.1 Reshape the current MPEG-4 SP CAL decoder according to the current FU interface in RVC WM
[ISO/IEC MPEG contribution] Report on results of RVC CE 2.2: Explore the extensibility of FUs
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Lossy compression of TPC data and trajectory tracking efficiency for the ALICE experimentNuclear Instruments & Methods in Physics Research Section a-Accelerators Spectrometers Detectors and Associated Equipment. 2003. Vol. 500, num. -2, p. 412-420. DOI : 10.1016/S0168-9002(03)00343-7.
An interpreted approach to multimedia streams protection2002. Eusipco 2002, Toulouse, September 2002. p. 63-66.
A System-on-a-chip for Multimedia Stream Processing and Communication2000.
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