Cosimo Aprile (2018)

Research Interests:

  • Analog/mixed-signal integrated circuits design

Biography

Cosimo Aprile was born in Leverano, Italy in 1988. He received the bachelor degree in Electronic Engineering in July 2010 from Politecnico di Torino. During the third academic year (2009/2010) he studied at Institut National des Sciences Appliquées de Lyon (INSA) in France.  He received the international M.Sc. in Micro and Nanotechnologies for ICTs which is a double degree between the Politecnico di Torino (Polito) and Institut National Polytechnique de Grénoble (INPG) and a joint degree with the École polytechnique fédérale de Lausanne (EPFL).  From March 2012 up to March 2013 he was employed by IBM Zurich Research Laboratory. In this period he worked for the Master Thesis project under the supervision of Professor Leblebici (EPFL) and Doct. Thomas Toifl (IBM). The task was the design of a low power receiver in 32nm SOI-CMOS able to efficiently remove far end crosstalk in single ended  wireline communication systems. Cosimo was a PhD student at LIONS from April 2013 to August 2018. His PhD theses entitled Learning-Based Hardware Design for Data Acquisition Systems was supervised by Professor Volkan Cevher and co-advised by Professor Leblebici.

Publications with LIONS (most recent)

A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS

A. Uran; K. Türe; C. Aprile; A. Trouillet; F. Fallegger et al. 

IEEE Journal of Solid-State Circuits. 2022.  p. 1-1. DOI : 10.1109/JSSC.2022.3161296.

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A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS

A. Uran; K. Ture; C. Aprile; A. Trouillet; F. Fallegger et al. 

2021-05-17. 2021 IEEE Custom Integrated Circuits Conference (CICC), Virtual, April 25-30, 2021. DOI : 10.1109/CICC51472.2021.9431458.

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

Ieee Journal Of Solid-State Circuits. 2020-01-01. Vol. 55, num. 1, p. 38-48. DOI : 10.1109/JSSC.2019.2938414.

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A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

2019-01-01. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 239-240. DOI : 10.1109/A-SSCC47793.2019.9056940.

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A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

J. Narinx; R. Giterman; A. Bonetti; N. Frigerio; C. Aprile et al. 

2019-01-01. 15th IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, PEOPLES R CHINA, Nov 04-06, 2019. p. 219-222. DOI : 10.1109/A-SSCC47793.2019.9056985.

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A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

2019-01-01. IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, Feb 17-21, 2019. p. 476-478. DOI : 10.1109/ISSCC.2019.8662505.

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Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

2018-05-04. Circuits and Systems (ISCAS), 2018 IEEE International Symposium on, Florence, Italy, 27-30 May 2018. DOI : 10.1109/ISCAS.2018.8350924.

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An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems

C. Aprile; J. Wuthrich; L. Baldassarre; Y. Leblebici; V. Cevher 

2018-01-01. 15th ACM International Conference on Computing Frontiers, Ischia, ITALY, May 08-10, 2018. p. 228-231. DOI : 10.1145/3203217.3203260.

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Real-time DCT Learning-based Reconstruction of Neural Signals

R. Karimi Mahabadi; C. Aprile; V. Cevher 

2018. 26th European Signal Processing Conference (EUSIPCO 2018), Rome, Italy, September 3-7. 2018. DOI : 10.23919/EUSIPCO.2018.8553402.

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Adaptive Learning-Based Compressive Sampling for Low-power Wireless Implants

C. Aprile; K. Ture; L. Baldassarre; M. Shoaran; G. Yilmaz et al. 

2018. 1st International Symposium on Integrated Circuits and Systems (ISICAS), Taormina, Italy, September 02-03, 2018. p. 3929-3941. DOI : 10.1109/TCSI.2018.2853983.

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