Workload- and hardware-aware transaction processing

The main goal for the “Workload- and hardware-aware transaction processing” proposal was to lay the groundwork for database systems that adapt and reconfigure online, depending on the workload and the hardware, while ensuring efficient resource utilization. In this project, we deliver fast and scalable algorithms which can be implemented with limited changes on existing On-Line Transaction Processing (OLTP) systems. We identify the fundamental computer architecture limitations that affect traditional OLTP systems, and establish a plan to permanently address these bottlenecks. Our approach does not require a fundamental redesign for OLTP databases, but suggests a set of fixes, which enables us to use the current hardware and software to its full potential.
According to the proposed directions, our research results are divided into four groups described in the paragraphs below. The first one comprises results from the exploration of the impact of non-uniform hardware topology on the transaction processing applications. The second and third groups are related to the efficient use of resources of the processor core by transaction processing systems, while the last one analyzes different aspects of energy efficiency.

The research leading to these results was funded by the Swiss
National Science Foundation (Project 200021 146407/1).

More Than A Network: Distributed OLTP on Clusters of Hardware Islands

D. Porobic; P. Tozun; R. Appuswamy; A. Ailamaki 

2016. 12th International Workshop on Data Management on New Hardware. DOI : 10.1145/2933349.2933355.

Characterization of the Impact of Hardware Islands on OLTP

D. Porobic; I. Pandis; M. S. De Oliveira Branco; P. Tozun; A. Ailamaki 

Vldb Journal. 2016. Vol. 25, num. 5, p. 625-650. DOI : 10.1007/s00778-015-0413-2.

ATraPos: Adaptive Transaction Processing on Hardware Islands

D. Porobic; E. Liarou; P. Tözün; A. Ailamaki 

2014. 30th IEEE International Conference on Data Engineering, Chicago, IL, USA, March 31 – Apr 4, 2014. p. 688-699. DOI : 10.1109/ICDE.2014.6816692.

A Methodology for OLTP Micro-architectural Analysis

U. Sirin; A. (. C. Yasin; A. Ailamaki 

2017-05-14. DAMON, Chicago, Illinois, May, 14 – 19, 2017. p. 1. DOI : 10.1145/3076113.3076116.

Micro-architectural Analysis of In-memory OLTP

U. Sirin; P. Tozun; D. Porobic; A. Ailamaki 

2016. SIGMOD 2016. p. 387-402. DOI : 10.1145/2882903.2882916.

Applying HTM to an OLTP System: No Free Lunch

D. Cervini; D. Porobic; P. Tozun; A. Ailamaki 

2015. The 11th International Workshop on Data Management on New Hardware, Melbourne, VIC, Australia, May 31 – June 04, 2015. DOI : 10.1145/2771937.2771946.

Dynamic Fine-Grained Scheduling for Energy-Efficient Main-Memory Queries

I. Psaroudakis; T. Kissinger; D. Porobic; T. Ilsche; E. Liarou et al. 

2014. 10th International Workshop on Data Management on New Hardware, Snowbird, Utah, USA, June 22-27, 2014. DOI : 10.1145/2619228.2619229.

OLTP on a server-grade ARM: power, throughput and latency comparison

U. Sirin; R. Appuswamy; A. Ailamaki 

2016. DAMON, San Francisco, California, 26 06 – 01 07 2016. p. 1-7. DOI : 10.1145/2933349.2933359.