Igor Stolichnov found proves for a thermodynamic intrinsic polarization reversal scenario in thin HZO films in a ferroelectric/dielectric heterostructure, a phenomenon with great implications for negative-capacitance-enhanced steep-slope devices.
Check out the publication in Applied Physics Letter.
Andrei Müller has found that in the case of VO2 filters a precise accurate modeling of RF performances needs to include the temperature history of the devices in case the transition temperature of the VO2 thin film is crossed.
Check out the publication in Applied Physics Letters.
Andrei Müller presented the evolution of the 2D Smith chart to the 3D Smith chart. New insights of negative capacitance, Vanadium dioxide RF modelling are also described.
Check out the the article in IEEE Microwave Magazine.
Matteo Cavalieri recently proposed a CMOS-compatible PLD fabrication route to deposit Hf-based ferroelectric thin films on a conventional TiN substrate with comparable properties to conventional ALD films.
Check out the publication on ACS Applied Electronic Materials.
Francesco Bellando has investigated the application of the Negative Capacitance effect to increase the current sensitivity of an ISFET. The resulting device noticeably outperforms the baseline sensor in terms of Subthreshold Swing, showing a viable solution to increase the precision of miniaturized chemical sensors.
Check out the publication on Applied Physics Letters.
Nicolò Oliva recently showed a p-type TFET co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform. The tunneling device clearly outperforms the 2D MOSFET in the subthreshold region, crossing its characteristic over several orders of magnitude of the output current and providing better digital and analog figures of merit.
Check out the publication on Nature.
Andrei Müller recently extracted the radio-frequency dielectric constant and loss of vanadium dioxide and Ge-doped vanadium dioxide thin films on SiO2/Si substrates using an original methodology based on Peano space filling curves.
Check out the publication on ACS Applied Electronic Materials.
Ali Saeidi successfully managed to combine Negative Capacitance of ferroelectrics with quantum band-to-band tunneling of TFETs and experimentally demonstrate a double beneficial effect: (i) a super steep SS down to 10mV/decade and an extended low slope region due to the NC effect and, (ii) a remarkable off-current reduction that is explained by the effect of ferroelectric’s dipoles.
Check out the publication on Nanoletters.
Clarissa Convertino recently demonstrated for the first time sub-thermionic TFETs integrated on Si (100). The devices are fabricated using a scalable Si CMOS-compatible FinFET-like process flow, enabling scaling of both gate lengths and fin dimensions. This work shows the feasibility of the implementation of scalable sub-thermionic TFETs in future ultra-low power logic nodes.
Check out the publication on IEEE Xplore (work presented at IEDM 2019, San Francisco, CA, USA).
Luca Capua presented his conference paper (co-authored by Yann Sprunger) titled ‘Double-Gate Si Nanowire FET Sensor Arrays For Label-Free C-Reactive Protein detection enabled by antibodies fragments and pseudo-super-Nernstian back-gate operation’ at IEDM 2021, in San Francisco.
Clara Moldovan awarded the Musy award for entrepeneurship, supporting her to transfer the novel energy storage technology developed in Nanolab to address an essential market application today. She led the development of high density supercapacitors based on aligned carbon nanotubes structures, which due to their high surface area and to the device design and optimized processes can store very high energy levels, removing the performance gap between batteries and supercapacitors while charging ultra-fast, extending the lifetime and use environmentally friendly materials. This allows the resulting spin-off, Swistor, to offer a competitive energy storage solution.
Yogesh Chauhan 2021 IEEE Fellow. Piscataway, New Jersey, USA, January 2021: former member of Nanolab Yogesh Chauhan, from Kanpur, Uttar Pradesh, India, has been named an IEEE Fellow, being recognized for contributions to compact modeling of Si and GaN transistors.
Professor Adrian M. Ionescu appointed to Proceedings of IEEE Editorial Board. In its last meeting the IEEE Publication Services and Products Board fully endorsed the appointment of our lab director, professor Ionescu, as a member of the Editorial Board of the Proceedings of the IEEE, effective 1 January 2021 through 31 December 2023. The Proceedings of the IEEE is one of the most distinguished journals serving the engineering profession. It is the IEEE leading journal to provide in-depth review, survey, and tutorial coverage of the technical developments in electronics, electrical engineering, and computer science.
Luca Capua will hold an e-poster presentation on “Antibodies fragments as capturing sites to enhance cardiac troponin detection (cTn) in Extended Gate Metal-Oxide-Semiconductor Field Effect Transistors (EGFET)” at the ESC Congress 2020, Amsterdam, NL.
Matteo Cavalieri is giving a presentation on “Fabrication of ferroelectric Gd:HfO2 by pulsed laser deposition in a CMOS compatible process” at the IFCS-ISAF 2020, Keystone, CO, USA.
A paper written by Nicolò Oliva, “WSe2/SnSe2 vdW heterojunction Tunnel FET with subthermionic characteristic and MOSFET co-integrated on same WSe2 flake” was published on Nature. The paper shows a p-type TFET co-integrated on the same flake with a p-type MOSFET in a WSe2/SnSe2 material system platform, which represents the new state-of-the-art in the field.
Clarissa Convertino, Carlotta Gastaldi and Nicolò Oliva are giving their presentations on Dec 10th (session 23) and 11th (session 37) at IEDM, San Francisco, CA, USA.
The Nanolab article “A novel reconfigurable CMOS compatible Ka band bandstop structure using split-ring resonators and Vadandium Dioxide (VO2) phase change switches” obtained the third place-award for the “Sixty-Second Presentation (S2P) Competition” at 2019 IEEE MTT-S International Microwave Symposium in Boston, USA.
Our video at the sixty second presentation competition at IMS, Boston
A paper co-authored by Ali Saeidi has won the 2017 Electron Devices Society George E. Smith Award. The paper is entitled “Negative Capacitance as Performance Booster for Tunnel FETs and MOSFETs: An Experimental Study”. The paper was co-authored by Farzan Jazaeri, Francesco Bellando, Igor Stolichnov, Gia V. Luong, Qing-Tai Zhao, Siegfried Mantl, Christian C. Enz, and Adrian M. Ionescu. The award will be presented at the IEEE International Electron Devices Meeting (IEDM) on Monday, December 3, 2018.
Prof. Ionescu has contributed to the IEEE International Electron Devices Meeting (IEDM) 2017 held in San Francisco (USA) with a plenary talk on Energy efficient computing and sensing in the Zettabyte era: from silicon to the cloud.
NanoLab has presented three conference papers during the 47th European Solid-State Device Research Conference ESSDERC2017:
Prof. Mihai Adrian Ionescu has been awarded an ERC Advanced Grant 2015. These grants are designed to allow outstanding research leaders of any nationality and any age to pursue ground-breaking, high-risk projects in Europe. The scheme targets researchers who have already established themselves as top independent research leaders.
The ESSDERC – ESSCIRC 2016 conference will be organized by EPFL at the Swisstech Convention Centre from 12 to 15 Septermber 2016. Prof. Adrian Ionescu along with Prof. Christian Enz will act as the general chair for this conference.
Click here for the first call for papers.
New master thesis projects available for 2015-2016 spring semester are now updated. Check here for details.
Prof. Adrian Ionescu will contribute to the “Beyond CMOS workshop” on Oct. 16-17, 2014 organised by IMEC Academy in IMEC, Leuven, Belgium. He will be delivering an invited lecture on Tunnel FETs titled “The steep end of the technology roadmap of semiconductors”.
Prof. Adrian Ionescu is coordinating a new European research project dubbed E2SWITCH. The project has revealed details about its plans to develop a next-generation chip technology called tunnel field-effect transistors (TFETs). The project also includes IBM, Forschungszentrum Jülich, the University of Lund, ETHZ, Imec, CCS, SCIPROM and IUNET. The project has been funded for up to 4.3 million euros over 42 months.
Prof. Adrian Ionescu delivered a talk titled “The wireless future of medicine: How digital revolution will create better healthcare” at the “Healthcare Revolution: Big Data and Smart Analytics” conference organised by Swiss Re Centre for Global Dialogue and GDI Gottlieb Duttweiler Institute on 12 March 2014.
The final e‐BRAINS Workshop on: “Heterogeneous 3D integration of sensors and circuits for Smart Microsystems” was organized by Prof. Adrian Ionescu on Feb. 17, 2014 at EPFL in Lausanne. The e-BRAINS workshop included a series of excellent technical contributions both by consortium members and by external speakers. More than 30 international workshop attendees followed technical presentations which are also available for download.
Prof. Adrian Ionescu has contributed to the IEDM Short Course “Beyond CMOS: Emerging Materials and Devices” on Dec. 8, 2013 in Washington DC, delivering an invited lecture on Tunnel FETs covering “steep slope” device concepts, sub-10mV/decade switches, active gate switching, NEM relays and negative capacitance devices.
Workshop satellite to ESSDERC/ESSCIRC 2013 : September 20th 2013, Bucharest – Romania
During the 43rd ESSDERC/ESSCIRC conference in Bucharest, Romania, the Guardian Angels consortium organized a workshop titled “In the quest for Zero-Power: Technologies and Applications”.
Workshop Presentations (Restricted Access)
Prof. Adrian Ionescu presented a talk titled “‘Zero power smart systems” at the Swissnex Boston in the framework of AAAS.
The American Association for the Advancement of Science (AAAS) is the world’s largest general scientific society. The 2013 AAAS Annual Meeting was held in Boston under the theme “The Beauty and Benefits of Science”. It highlighted the “unreasonable effectiveness” of the scientific enterprise in creating economic growth, solving societal problems, and satisfying the essential human drive to understand the world in which we live.
Nanolab is an active member of the NANOHEAT Project (Framework 7 STREP) which is a three-year project funded by the European Commission, aimed at providing integrated platform for multidimensional nanoprobing and advanced therml analysis at the nanoscale has been launched. The principle goal of the NANOHEAT is to adevelop, deliver and test a miniaturized and integrated platform which provides a multidimensional nanoprobing capabilities for advanced thermal analysis at the nanoscale. The NANOHEAT Project Consortium is based on complementary expertise and facilities of nine partners from four different European countries.
[press note; for more info visit NANOHEAT]
Nanolab organized and coordinated a tutorial and workshop in ESSDERC/ESSCIRC 2012 at Bordeaux, France:
EU STEEPER project workshop: Steep Slope Switches (SSS) Technologies, Devices, Applications
Zero power technologies for Autonomous Smart Systems : 19-20th March San Francisco USA Workshop
During 19-20th March 2012 in San Francisco, California, the Guardian Angels consortium in cooperation with the University of California, Berkeley and Swissnex organized a workshop on Zero power technologies for Autonomous Smart Systems.
Download the GA Workshop program
Nanotech 2012 February 15-17, 2012; Conference Tower, Tokyo Big Sight, Japan.
Embed of video is only possible from Mediaspace, SwitchTube, Vimeo or Youtube
The Science & Technology Office Tokyo organized the Swiss Science Corner at the Swiss Pavilion during “nano tech 2012” in Tokyo, which is the world’s largest nanotechnology expo with over 45’000 visitors. Professor Adrian Ionescu, together Dr. Gerard Escher (EPFL) and Dr. Heike Riel (IBM Research Zurich) gave presentations on the “Guardian Angels” initiative, seeking collaboration opportunities with Japanese academia and industry. The GA seminar was joined by 40 high-level participants. Among them, six FIRST Program owners participated. FIRST is a top-level program of Japan and the acronym for “Funding Program for World-Leading Innovative R&D on Science and Technology”.
Professor Adrian Ionescu, together with professor David Jimenez of the UAB (Universitat Autònoma de Barcelona) organized the Workshop on Energy Efficient Electronic Technologies and Systems (E3TS) in Barcelona on July 18 and 19.
On May 5th, at the FET 11 conference in Budapest, Prof Adrian Ionescu presented “Guardian Angels for a Smarter Life” to the scientific community.
Here is what the Financial Times had to say: “Perhaps the most futuristic proposal is EPFL’s Guardian Angels, which will use computing and imaginative energy research to “create the ultimate smart device that will assist humans from infancy to old age”. The guardian angel will “scavenge for energy” from its environment, for example by tapping the heat and movements of the human body, said Adrian Ionescu, project leader.”
FET 11 – Professor Ionescu presenting the Guardian Angels project (photo)
FET 11 – Flagship Pilot award ceremony – six finalists (photo)
European researchers chase billion-euro technology prize: Professor Adrian Ionescu leads, in collabora- tion with ETH Zurich, the Guardian Angels project, one of the six futuristic FET Flagship proposals selected by European Commission. The victors expect to receive an unprecedented level of funding for academia: €1 billion Euros over the next decade.
Devices physics strikes back: Tunnel FETs to battle dark silicon: An interview given by professor Adrian Ionescu: Towards a ten-fold increase in electronic device efficiency .
Eliminating Vampire Power: Nanolab starts coordination of European Union “Steeper Project “ – aiming to boost electronics’ power efficiency by 10 times and eliminate vampire power.
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Nanolab is an active member of the FP7 NANO-TEC project (EU-ICT project no. 257964) seeking to build a community of academic researchers in nanoelectronics, addressing specifically research in Beyond CMOS from the combined technology and design perspectives. A methodology for continued consultation and analysis of research needs and trends will be developed. The main activity will be a workshop series with invited experts, preceded by a methodology-contents preparation phase and subsequent analysis and documentation, both by the consortium. Apart of determining what is relevant for Beyond CMOS devices and design, benchmarking and SWOT analyses will be performed.