Masters and Semester Projects

What we do at VLSC in a nutshell.

At the Very Large Scale Computing (VLSC) we are developing Manticore, a many-core machine to accelerate RTL simulation (e.g., Verilog or VHDL).  A 225-core Manticore machine accelerates RTL simulation by up to 27x compared to state-of-the-art existing simulators (e.g., ModelSim or Verilator) by taking advantage of massive on-chip parallelism.
We have a fully functional hardware prototype and a custom Verilog compiler all built in-house. However, there are still many design choices we wish to evaluate and features to add, both in hardware and software. This is where you can help!
The projects regarding Manticore will offer you a unique opportunity to dive into a large project, spanning both hardware and software, and make an impact on the final quality of results. If you like compilers and hardware, look no further! We have plenty of interesting problems you can solve!



Here you can find list of potential projects and topic you could work on. All projects are directly or indirectly related to Manticore. They could be taken as both masters and semester projects (we will adjust the goals accordingly) unless stated otherwise.


If you are interested in any of the projects or want to know more, do not hesitate to contact Mahyar Emami ([email protected]) for more information.

1. Accelerator Benchmark Suite

This project is hardware-oriented.

There is great momentum in “hardware-compilers” research, for instance, `circt`(Circuit IR Compilers and Tools) tries to bring in hardware compilers into the LLVM infrastructure to benefit from the modularity of optimization passes LLVM offers. `Calyx` from Cornell is another attempt separate control and datapath optimizations for improved quality of results. Unlike software, that have longed enjoyed access to comprehensive benchmark suites, hardware compilers do not enjoy access to a shared benchmark suite of accelerator design.
We already have a small set of accelerators, you can help us by bringing more to the table and potentially make an impact in the research community.
This project is indirectly related to Manticore, but can help further develop and optimize Manticore hardware to make it even faster with a fresh set of workloads.
  • Develop a suite of accelerators from different domains using readily available software descriptions through hardware compilers or open-source hardware projects.
  • Develop testbenches for each accelerator.
  • Familiarity with at least one hardware description language (Verilog, VHDL, Chisel) is a must (ideally you should have had taken a course similar to CS-208).
  • Basic scripting skills (Python, GNU Make, Bash, and etc.)

 2. Debugging Capabilities for Manticore

This project is requires both hardware and software experience. This project is mostly suitable for a master student.

The main job of an RTL simulator is to test and debug a hardware design. Our current Manticore prototype has little support for advanced debugging capabilities such as breakpoints or waveforms.

We have some ideas how to implement these features and you can help us carry them out. This project is a difficult, yet rewarding one. The first step is to implement waveform debugging and then perhaps a more advanced breakpoint debugging flow.

  • Develop hardware and software to enable waveform debugging in Manticore
  • Develop hardware and software to enable breakpoint debugging in Manticore
  • Familiarity with at least one hardware description language (e.g., VHDL or Verilog)
  • Familiarity with Scala
  • Some familiarity with C++

3. FPGA Network-on-Chip Implementation

This project is hardware-oriented but requires software skills as well.

Our current Manticore hardware connects the few hundreds of cores it has with a simple 2-D uni-directional torus network-on-chip (NoC). We wish to explore other network topologies (such as a fat butterfly)on a high-end FPGA and evaluate their performance (e.g., maximum achievable clock frequency, latency, bandwidth, and etc.)

  • Improve Manticore’s performance by an intelligent NoC design
  • Hardware design experience (e.g., Verilog)
  • FPGA experience
  • Knowledge of Chisel and Scala is a plus

4. More DRAM for Manticore

This project is hardware-oriented.

Manticore’s ISA provides strong latency guarantees for every instruction. This makes accessing off-chip memories (DRAM) with non-deterministic access times tricky to implement. Currently, we have a mechanism to mask the non-deterministic access of a single DRAM bank. We would like to extend the current approach or explore alternatives to connect more DRAM banks (hopefully 3 or 4).

  • Extend Manticore’s microarchitecture implementation to support multiple DRAM banks
  • Strong background in hardware
  • FPGA experience
  • Familiarity with Chisel is a plus

5. Verilog DPI support in Manticore

This project is software-oriented.

Our current Manticore compiler supports basic Verilog system calls such as $display and $stop. We want to extend the support for arbitrary DPI (Direct Programing Interface) calls using the new or existing mechanism.

  • DPI support in Manticore
  • Basic understanding of a C/C++ build tool (e.g., CMake, Make, and etc.)
  • Intermediate C++ and Scala skills