Feedback-friendly clock tree synthesis for AQFP circuits.

Availability: Spring-Summer 2023

Contact: Rassul Bairamkulov ([email protected])


Superconductive electronics (SCE) is a promising candidate for supplementing or replacing existing CMOS VLSI systems. An Adiabatic Quantum-Flux-Parametron is an extremely low power superconductive technology with speeds on the order of tens of GHz. An issue rarely addressed in the literature is the feedback paths in AQFP circuits which are challenging in a fully clocked environment [1]. Three primary issues complicate the data and clock paths in AQFP circuits

  • feedback loops typically need to be of equal length (in terms of pipeline stages),
  • phases should be aligned along any data path,
  • clock skew should be either minimized or managed to ensure correct data transfer.

Several clocking topologies however exist that tackle these issues and provide more flexibility for datapaths and clock distribution.

Project tasks:

  • Simulation of simple AQFP circuits using VerilogA or specialized simulation tools, such as WRSPICE, JSIM, or JoSIM
  • Development of prototypical AQFP circuits and clock distribution networks
  • Evaluation of the AQFP circuits using HDL-based simulation tools


  • Basic knowledge of 
    • circuit simulation tools (e.g. Cadence Virtuoso or any version of SPICE)
    • hardware description langugages
  • Proficiency in sequential circuit design

Learning outcomes:

  • Introduction to
    • superconductive electronics
    • standard cell design
    • logic synthesis
  • Experience in
    • circuit analysis
    • optimization tools
    • command line interface

Related literature:

Paper tackling feedback in AQFP

[1] Takeuchi, N., Ayala, C. L., Chen, O., & Yoshikawa, N. (2019). A feedback-friendly large-scale clocking scheme for adiabatic quantum-flux-parametron logic datapaths. IEEE Transactions on Applied Superconductivity, 29(5), 1-5.

Introduction to AQFP technology (see background sections)
[2] Lee, S. Y., Riener, H., & De Micheli, G. (2021). Irredundant buffer and splitter insertion and scheduling-based optimization for AQFP circuits. arXiv preprint arXiv:2109.00291.

[3] Cai, R., Chen, O., Ren, A., Liu, N., Yoshikawa, N., & Wang, Y. (2019). A buffer and splitter insertion framework for adiabatic quantum-flux-parametron superconducting circuits. In 2019 IEEE 37th International Conference on Computer Design (ICCD) (pp. 429-436). IEEE.