Availability: Spring-Summer 2023
Contact: Rassul Bairamkulov ([email protected])
Background:
In traditional VLSI power delivery networks, the on-chip supply voltage is provided by board-level converters. Due to the significant distance between the converter and the load, variations in the load current are not effectively managed, producing a significant voltage drop at the point-of-load.
To mitigate this issue, modern high performance systems utilize on-chip voltage regulators. Due to the close proximity to the load, these regulators can quickly respond to fluctuations in the input voltage or load current, providing superior power quality.
Integrated voltage regulators however require significant area, limiting the number of on-chip regulators.
The regulators therefore have to be judiciously placed within an IC layout to maximize the power quality with minimum area. During the optimization process, the circuit is analyzed hundreds or thousands of times, necessitating a circuit analysis. The size of the modern on-chip power grids however poses a major difficulty, since the accurate analysis is prohibitively expensive in terms of time and hardware.
Several works in the literature propose algorithms for placing the on-chip regulators within an IC. The placement algorithm in [1] determines good placement through transient simulations, and is therefore not scalable. The algorithms in [2-3] use approximate models of the power grid, providing good results at the cost of degraded accuracy.
Many methods exist to accelerate the circuit analysis [4]. In particular, since the circuit is incrementally changed during the optimization process, iterative methods can be effective to accelerate the optimization process. Other methods, such as multigrid and circuit partitioning can also be effective.
Project tasks:
- Implement a DC linear circuit analysis tool based on modified nodal analysis (using Python or C++)
- Apply iterative methods (and, potentially, other methods) to accelerate DC simulation exploiting incremental changes in topology.
- Integrate the iterative analysis method with the optimization algorithms.
Requirements:
- Theoretical understanding of
- linear matrix equations
- circuit analysis
- Proficiency with Python or other programming language
- High-level understanding of optimization process and tools
Learning outcomes:
- Introduction to VLSI power network design
- Advanced circuit analysis and optimization
Related literature:
Transient analysis-based placement of voltage regulators
[1] Yu, T., & Wong, M. D. (2014). Efficient simulation-based optimization of power grid with on-chip voltage regulator. In 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 531-536)
Placement based on compact models
[2] Bairamkulov, R., & Friedman, E. (2022). Placement of on-chip distributed voltage regulators. In Graphs in VLSI (pp. 217-236). Cham: Springer International Publishing.
[3] Sadat, S. A., Canbolat, M., & Köse, S. (2018). Optimal allocation of LDOs and decoupling capacitors within a distributed on-chip power grid. ACM Transactions on Design Automation of Electronic Systems (TODAES), 23(4), 1-15.
A book chapter with an overview of circuit analysis methods
[4] Bairamkulov, R., & Friedman, E. (2022). Circuit analysis. In Graphs in VLSI (pp. 149-176). Cham: Springer International Publishing.
For more information, please contact Rassul Bairamkulov [email protected]