Dynamatic is an academic, open-source high-level synthesis compiler that produces synchronous dynamically-scheduled circuits from C/C++ code. Dynamatic generates synthesizable RTL which currently targets Xilinx FPGAs and delivers significant performance improvements compared to state-of-the-art commercial HLS tools in specific situations (e.g., applications with irregular memory accesses or control-dominated code).
Dynamatic is available at https://dynamatic.epfl.ch/.
Lana Josipović, Radhika Ghosal, and Paolo Ienne. Dynamically scheduled high-level synthesis. In Proceedings of the 26th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 127-36, Monterey, Calif., February 2018. Best Paper Award Nominee.
DynaBurst is a highly flexible, FPGA-optimized, multi-banked nonblocking cache that uses bursts as much as possible to transfer data from external memory. The block RAM-based MSHRs (miss status holding registers) can support tens of thousands of outstanding misses, maximizing the reuse of each memory response before it is even stored in the cache, increasing the performance of bandwidth-bound, latency insensitive accelerators. Using bursts increases the available bandwidth by reducing DDR row conflicts and increasing the utilization of DDR bursts.
DynaBurst is available at https://github.com/m-asiatici/dynaBurst.
Mikhail Asiatici and Paolo Ienne. DynaBurst: Dynamically Assemblying DRAM Bursts over a Multitude of Random Accesses. In Proceedings of the 29th International Conference on Field-Programmable Logic and Applications, pages 254–62, Barcelona, September 2019.
LEOSoC is an open-source cross-platform embedded Linux library to manage reconfigurable hardware accelerators in heterogeneous System on Chips. LEOSoC reduces the development effort required to interface hardware accelerators with applications and making SoCs easy to use for an embedded software developer who is familiar with the semantics of standard POSIX threads.
LEOSoC is available at https://github.com/Andrea-Guerrieri/LEOSoC.
Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici and Paolo Ienne. “Snap-On User-Space Manager for Dynamically Reconfigurable System-on-Chips” in IEEE Access, vol. 7, pp. 103938-103947, 2019.
See also: [AHS’18]
FPRESSO is an automatic FPGA modeling tool, that is used to model the delay and area of a given FPGA architecture. When provided with a description of the architecture, FPRESSO uses standard-cell tools and an extensive library of FPGA building blocks to size the FPGA components and return a VTR-compatible FPGA architecture file, fully annotated with area and delay values.
FPRESSO is available on request. Please contact us.
FPRESSO is temporarely not available at http://fpresso.epfl.ch.
Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, and Paolo Ienne. FPRESSO: Enabling express transistor-level exploration of FPGA architectures. In Proceedings of the 24th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, pages 80-89, Monterey, Calif., February 2016. Best Paper Award.