A C-RAN-Based Mitigation of Reactive Jamming Attacks in LoRa Networks with Jamming Cancellation

A. Dossa; J. Tapparel; A. Burg; E. M. Amhoud 

HDPC Codes with LDPC Matrices: Construction Based on Social Golfer Problem

Y. Shen; H. S. Ünal; A. Burg 

Dynamic Dual-Window Decoding for SC-LDPC Codes with Wave Enhancement

L. Zhang; Y. Ren; A. Burg 

CIM-FLEX: An Integer-Only Flexible Periphery for Distributed Compute-In-Memory Architectures

İ. Şanlı; M. Rossi; E. Ferro; A. Jha; A. P. Burg et al. 

A 2.35mm2 118.3Gbps 5.14pJ/Bit Dual-Mode LDPC Decoder for 5G/6G

Y. Ren; Y. Wang; L. Zhang; W. Song; L. Blanc et al. 

Top-Metal-Only RFIC Retargeting for Fast Specs-To-Silicon Iteration Enabled by AI-Assisted Inverse Design

C. Chu; Y. Liu; Y. Xu; S. Fu; T. Torii et al. 

Proof of Concept of QCSP Frames in Earth-to-LEO Satellite Transmission

L. M. Obeso; S. Tannir; C. Roland; E. Boutillon; H. Boeglen et al. 

A Full-Custom Time-Domain Unary Sorter for Soft-Information Decoding in 65 nm CMOS

M. Cancalon; L. D. Blanc; C. Muller; Y. Wang; A. Burg 

Enabling Reliable and Scalable LoRa with Collision Resolution and Centralized Radio Access

Turbo Product Code-aided Spatiotemporal 2-d Coded Mimo for Urllc

Y. Tian; J. Zheng; Z. Li; T. Xia; Y. Shen et al. 

GenPolar: Generative AI-Aided Complexity Reduction for Polar SCL Decoding

Y. Sun; J. Chen; Y. Ren; H. Ji; Y. Huang et al. 

Toward Universal Belief Propagation Decoding for Short Binary Block Codes

Y. Shen; Z. Li; Y. Ren; E. Boutillon; A. Balatsoukas-Stimming et al. 

Edge-Spreading Raptor-Like LDPC Codes for 6G Wireless Systems

Y. Ren; L. Zhang; Y. Shen; W. Song; E. Boutillon et al. 

Device-Free Floor-Scale Human Detection With Indoor LTE Antennas

S. Li; A. Balatsoukas-Stimming; A. Burg 

HDD-RAM: A 40-nm 0.35V 25MHz Half-Select Disturb-Free Memory with Data-Aware 10T SRAM

Y. Li; J. Chen; Y. Wang; W. Zhao; Y. Shu et al. 

TRIP: Tree Search-Based Iterative Detection and Decoding for Polar-Coded MIMO Systems

J. Chen; Y. Sun; Y. Shen; Y. Huang; X. You et al. 

A Universal LDPC Matrix for Short-Length Codes and Long-Length Codes

Y. Ren; L. Zhang; E. Boutillon; A. Balatsoukas-Stimming; A. Burg 

Decoding Product Codes with Belief Propagation

Y. Shen; Z. Li; Y. Ren; E. Boutillon; C. Zhang et al. 

A 5.9 μJ/Inference Reconfigurable Accelerator for Hybrid SNN-ANN Architectures in Event-based Image Recognition

C. Sun; B. Jia; Q. Chen; W. Song; J. Qian et al. 

Impact of Reactive Jamming Attacks on LoRaWAN: a Theoretical and Experimental Study

A. Dossa; A. Burg; E. M. Amhoud 

Efficient Ordered Statistics Decoder with Unfolded Gaussian Elimination

L. Zhang; Y. Ren; C. Zhang; A. Burg; Y. Shen 

Benchmark of EEG-based seizure detection algorithms with SzCORE

C. W. Samanos; J. Dan; D. Atienza Alonso 

An Ultra Low Power Analog/Mixed-Signal Processor for a Smart RF Signal Classification System in the ISM Band

N. Pekcokguler; C. Dehollain; A. Burg; P. Courouve; D. Morche 

An SDR-Based Monostatic Wi-Fi System with Analog Self-Interference Cancellation for Sensing

A. T. Kristensen; A. Balatsoukas‐Stimming; A. P. Burg 

Belief Propagation Decoding for Short Codes on Structured Sparse Parity-Check Matrices

Y. Shen; Z. Li; E. Boutillon; W. Song; Y. Ren et al. 

Enhancing Channel Decoding Through Full-Custom Hardware Design

L. D. Blanc; A. Cardinale; W. Song; Y. Shen; C. T. Müller et al. 

Iterative Logistic Weight Based Chase Decoder for Open Forward Error Correction

Y. Shen; W. Song; L. D. Blanc; Y. Ren; A. Balatsoukas-Stimming et al. 

Dataset and UAV Propagation Channel Modeling for LoRa in the 860 MHz ISM Band

J. T. Tapparel; A. P. Burg 

Vital Signs and Human Activity Sensing with Wireless Systems

Design, Optimization and Verification of Embedded Gain Cell RAMs

Efficient Algorithms and VLSI Implementations of FEC Decoders for B5G/6G

Monostatic Wi-Fi Sensing: Self-Interference Cancellation and Channel Splicing for Robust Vital-Sign Monitoring

Dynamic gain cell with reduced leakage

R. Giterman; A. P. Burg; H. A. Yigit 

Optimizing Polar Codes for Reduced Latency Successive Cancellation List Decoder

H. Zhou; Y. Ren; J. Li; W. J. Gross 

Belief Propagation Decoding for Short-Length Codes Based on Sparse Tanner Graph

Z. Li; Y. Shen; y. ren; Y. Huang; X. You et al. 

A High Dynamic Range Envelop Detector for Heterodyne Receiver Architecture

N. Pekcokguler; D. Morche; A. Burg; C. Dehollain 

A Generalized Adjusted Min-Sum Decoder for 5G LDPC Codes: Algorithm and Implementation

Y. Ren; H. Harb; Y. Shen; A. Balatsoukas-Stimming; A. Burg 

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

R. Golman; R. Giterman; A. Teman 

A Node-Based Polar List Decoder With Frame Interleaving and Ensemble Decoding Support

Y. Ren; L. Zhang; L. D. Blanc; Y. Shen; X. Li et al. 

High-Throughput and Flexible Belief Propagation List Decoder for Polar Codes

Y. Ren; Y. Shen; L. Zhang; A. T. Kristensen; A. Balatsoukas-Stimming et al. 

A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time

O. Harel; A. Yigit; E. Feifel; R. Giterman; A. Burg et al. 

Centralized RAN for LPWAN: Architecture and Proof-of-Concept Prototype Implementation

J. Tapparel; A. Burg 

Towards 6G: Configurable High-Throughput Decoder Implementation for SC-LDPC Codes

Y. Ren; Y. Shen; W. Song; A. Balatsoukas-Stimming; E. Boutillon et al. 

LoRa Fine Synchronization with Two-Pass Time and Frequency Offset Estimation

J. T. Tapparel; A. P. Burg 

Learning-based Hand Gesture Classification using Channel Impulse Response with UWB

C. Samanos; H. Miao; S. Li; A. Balatsoukas-Stimming; A. Burg 

A GRANDAB Decoder with 8.48 Gbps Worst-Case Throughput in 65nm CMOS

L. D. Blanc; V. Herrmann; Y. Ren; C. Muller; A. T. Kristensen et al. 

Monostatic Multi-Target Wi-Fi-Based Breathing Rate Sensing Using Openwifi

A. T. Kristensen; S. Li; A. Balatsoukas-Stimming; A. Burg 

A Low-Latency and High-Performance SCL Decoder with Frame-Interleaving

L. Zhang; Y. Ren; Y. Shen; W. Zhou; A. Balatsoukas-Stimming et al. 

Intelligent RF System for Ultra Low Power Spectrum Sensing with Machine Learning

Belief-Selective Propagation Detection for MIMO Systems

W. Zhou; Y. Shen; L. Li; Y. Huang; C. Zhang et al. 

Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes

M. Hashemipour-Nazari; Y. Ren; K. Goossens; A. Balatsoukas-Stimming 

An Ultra-Low-Power Widely-Tunable Complex Band-Pass Filter for RF Spectrum Sensing

N. Pekcokguler; D. Morche; A. Burg; C. Dehollain 

A 128-kbit GC-eDRAM With Negative Boosted Bootstrap Driver for 11.3x Lower-Refresh Frequency at a 2.5% Area Overhead in 28-nm FD-SOI

A. Yigit; E. N. Casarrubias; R. Giterman; A. Burg 

Spreading Factor assisted LoRa Localization with Deep Reinforcement Learning

Y. Etiabi; M. Jouhari; A. Burg; E. M. Amhoud 

Increasing LoRa Sensitivity and Reliability with an IoT Cloud RAN

J. Tapparel; A. Burg 

Single-anchor Uwb Localization Using Channel Impulse Response Distributions

S. Li; A. Balatsoukas-Stimming; A. Burg 

Band-of-Interest-based Channel Impulse Response Fusion for Breathing Rate Estimation with UWB

S. Li; A. Balatsoukas-Stimming; A. Burg 

Improved Belief Propagation Decoding of Turbo Codes

Y. Shen; Y. Ren; A. T. Kristensen; X. You; C. Zhang et al. 

Low Power LDPC Decoding by Reliable Voltage Down-Scaling

J. Valkama; M. Safarpour; H. Dicander; Z. Deng; A. Burg et al. 

A Maximum-Likelihood-Based Two-User Receiver for LoRa Chirp Spread-Spectrum Modulation

M. Xhonneux; J. Tapparel; A. Balatsoukas-Stimming; A. Burg; O. Afisiadis 

Ultra-High-Throughput EMS NB-LDPC Decoder with Full-Parallel Node Processing

H. Harb; A. C. Al Ghouwayel; L. Conde-Canencia; C. Marchand; E. Boutillon 

Design for Test With Unreliable Memories by Restoring the Beauty of Randomness

R. Ghanaatian; M. Widmer; A. Burg 

A Low-Complexity LoRa Synchronization Algorithm Robust to Sampling Time Offsets

M. Xhonneux; O. Afisiadis; D. Bol; J. Louveaux 

Dynamic SCL Decoder With Path-Flipping for 5G Polar Codes

Y. Shen; A. Balatsoukas-Stimming; X. You; C. Zhang; A. P. Burg 

64-kB 65-nm GC-eDRAM With Half-Select Support and Parallel Refresh Technique

O. Harel; E. N. Casarrubias; M. Eggimann; F. Gurkaynak; L. Benini et al. 

A Sequence Repetition Node-Based Successive Cancellation List Decoder for 5G Polar Codes: Algorithm and Implementation

Y. Ren; A. T. Kristensen; Y. Shen; A. Balatsoukas-Stimming; C. Zhang et al. 

Increasing Cellular Network Energy Efficiency for Railway Corridors

A. Schumacher; R. Merz; A. Burg 

Beam Selection and Tracking for Amplify-and-Forward Repeaters

A. Schumacher; R. Merz; A. Burg 

List Ordered Statistics Decoders for Polar Codes

Z. Li; L. Zhang; Y. Shen; A. Burg; X. You et al. 

Fast Sequence Repetition Node-Based Successive Cancellation List Decoding for Polar Codes

Y. Shen; Y. Ren; A. T. Kristensen; A. Balatsoukas-Stimming; X. You et al. 

Cellular Fronthauling for Data Capacity Increase in Underserved Spaces

ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories

R. Ghanaatian Jahromi; R. Giterman; A. Bonetti; A. P. Burg 

Space Localisation

A. Zimmermann 

On the Advantage of Coherent LoRa Detection in the Presence of Interference

O. Afisiadis; S. Li; J. Tapparel; A. Burg; A. Balatsoukas-Stimming 

An Energy-Autonomous Wireless Sensor With Simultaneous Energy Harvesting and Ambient Light Sensing

R. La Rosa; C. Dehollain; A. Burg; M. Costanza; P. Livreri 

Adding Indoor Capacity without Fiber Backhaul: An mmWave Bridge Prototype

A. Schumacher; R. Merz; A. Burg 

Polarization-Adjusted Convolutional (PAC) Codes: Sequential Decoding vs List Decoding

M. Rowshan; A. Burg; E. Viterbo 

Enhancing the Reliability of Dense LoRaWAN Networks With Multi-User Receivers

J. Tapparel; M. Xhonneux; D. Bol; J. Louveaux; A. Burg 

Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads

Y. Weizman; R. Giterman; O. Chertkow; M. Wicentowski; I. Levi et al. 

Intrinsically Self-powered, Battery-free, and Sensor-free Ambient Light Control System

R. La Rosa; M. Costanza; A. Burg; C. Dehollain; P. Livreri 

ComplexBeat: Breathing Rate Estimation from Complex CSI

S. Li; A. T. Kristensen; A. Burg; A. Balatsoukas-Stimming 

A Novel RF Spectrum Monitoring Architecture for an Ultra-Low-Power Wi-Fi Geopositioning System

N. Pekcokguler; M. Maman; A. Burg; C. Dehollain; D. Morche 

Improving Railway Track Coverage with mmWave Bridges: A Measurement Campaign

A. Schumacher; N. Jamaly; R. Merz; A. Burg 

Dynamic Range and Complexity Optimization of Mixed-Signal Machine Learning Systems

N. Pekcokguler; D. Morche; A. Frischknecht; C. Gerum; A. Burg et al. 

Adaptive Body Biasing in Strong Body Factor Technologies

Le fil d’Ariane, redécouverte du Musée des Thermes et de Cluny à Paris

C. Boyer 

Replica Bit-Line Technique for Internal Refresh in Logic-Compatible Gain-Cell Embedded DRAM

O. Harel; Y. Nachum; R. Giterman 

Hardware Implementation of Neural Self-Interference Cancellation

Y. Kurzo; A. T. Kristensen; A. Burg; A. Balatsoukas-Stimming 

Artificial Intelligence for 5G and Beyond 5G: Implementations, Algorithms, and Optimizations

C. Zhang; Y-L. Ueng; C. Studer; A. Burg 

A Standalone FPGA-Based Miner for Lyra2REv2 Cryptocurrencies

J-F. Tetu; L-C. Trudeau; M. Van Beirendonck; A. Balatsoukas-Stimming; P. Giard 

Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space

R. Giterman; A. Bonetti; E. V. Bravo; T. Noy; A. Teman et al. 

Gain-Cell Embedded DRAMs: Modeling and Design Space

A. Bonetti; R. Golman; R. Giterman; A. Teman; A. Burg 

Design and Decoding of Irregular LDPC Codes Based on Discrete Message Passing

M. Meidlinger; G. Matz; A. Burg 

On the Error Rate of the LoRa Modulation With Interference

O. Afisiadis; M. Cotting; A. Burg; A. Balatsoukas-Stimming 

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

A 1-Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16-nm FinFET

R. Giterman; A. Shalom; A. Burg; A. Fish; A. Teman 

Coded LoRa Frame Error Rate Analysis

O. Afisiadis; A. Burg; A. Balatsoukas-Stimming 

A Maximum-Likelihood-based Multi-User LoRa Receiver Implemented in GNU Radio

M. Xhonneux; J. Tapparel; O. Afisiadis; A. Balatsoukas-Stimming; A. Burg 

Identification of Non-Linear RF Systems Using Backpropagation

A. T. Kristensen; A. Burg; A. Balatsoukas-Stimming 

Complexity-efficient Fano Decoding of Polarization-adjusted Convolutional (PAC) Codes

M. Rowshan; A. Burg; E. Viterbo 

On the Implementation Complexity of Digital Full-Duplex Self-Interference Cancellation

A. T. Kristensen; A. Balatsoukas-Stimming; A. Burg 

GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI

R. Giterman; A. Bonetti; A. Burg; A. Teman 

Gain-Cell Embedded DRAMs: Modeling and Design Space

A. Bonetti; R. Golman; R. Giterman; A. Teman; A. Burg 

Lupulus: A Flexible Hardware Accelerator For Neural Networks

A. T. Kristensen; R. Giterman; A. Balatsoukas-Stimming; A. Burg 

Training Channel Selection for Learning-based 1-bit Precoding in Massive MU-MIMO

S. Li; A. Burg; A. Balatsoukas-Stimming 

An Open-Source LoRa Physical Layer Prototype on GNU Radio

J. Tapparel; O. Afisiadis; P. Mayoraz; A. Balatsoukas-Stimming; A. Burg 

Energy- and Cost-Efficient VLSI DSP Systems Design with Approximate Computing

Physical Layer Aspects of LoRa and Full-Duplex Wireless Transceivers

GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI

R. Giterman; A. Bonetti; A. Burg; A. Teman 

2019 International Symposium on Low Power Electronics and Design

A. Burg; S. Mukhopdhyay; M. Ziegler 

Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection

R. Giterman; R. Golman; A. Teman 

Scalable Boolean Methods in a Modern Synthesis Flow

E. Testa; L. G. Amarù; M. Soeken; A. Mishchenko; P. Vuillod et al. 

Minimum Energy Point in Constant Frequency Designs under Adaptive Supply Voltage and Body Bias Adjustment in 55 nm DDC

C. T. Mueller; M. Pons; D. Ruffieux; J-L. Nagel; S. Emery et al. 

Neural-Network Optimized 1-bit Precoding for Massive MU-MIMO

A. Balatsoukas-Stimming; O. Castaneda; S. Jacobsson; G. Durisi; C. Studer 

LDPC Coded Multiuser Shaping for the Gaussian Multiple Access Channel

A. Balatsoukas-Stimming; S. Rini; J. Kliewer 

Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems

R. Ghanaatian; V. Jamali; A. Burg; R. Schober 

A 4.8pJ/b 6Gb/s ADC-Based PAM-4 Wireline Receiver Data -Path with Cyclic Prefix in 14nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications

J. Narinx; R. Giterman; A. Bonetti; N. Frigerio; C. Aprile et al. 

LoRa Symbol Error Rate Under Non-Aligned Interference

O. Afisiadis; M. Cotting; A. Burg; A. Balatsoukas-Stimming 

Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space

E. V. Bravo; A. Bonetti; A. Burg 

Power Analysis Resilient SRAM Design Implemented with a 1% Area Overhead Impedance Randomization Unit for Security Applications

R. Giterman; M. Wicentowski; O. Chertkow; I. Sever; I. Kehati et al. 

Advanced Machine Learning Techniques for Self-Interference Cancellation in Full-Duplex Radios

A. T. Kristensen; A. Burg; A. Balatsoukas-Stinuning 

A 0.5 V 2.5 mu W/MHz Microcontroller with Analog-Assisted Adaptive Body Bias PVT Compensation with 3.13 nW/kB SRAM Retention in 55 nm Deeply-Depleted Channel CMOS

M. Pons; C. T. Mueller; D. Ruffieux; J-L. Nagel; S. Emery et al. 

3.5 GHz Coverage Assessment with a 5G Testbed

A. Schumacher; R. Merz; A. Burg 

JESD204B Compliant 12.5 Gb/s LVDS and SST Transmitters in 28 nm FD-SOI CMOS

F. Celik; A. Akkaya; A. Tajalli; A. Burg; Y. Leblebici 

A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

G. Kim; L. Kull; D. Luu; M. Braendli; C. Menolfi et al. 

FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems

M. Widmer; A. Bonetti; A. Burg 

A Lyra2 FPGA Core for Lyra2REv2-Based Cryptocurrencies

M. van Beirendonck; L-C. Trudeau; P. Giard; A. Balatsoukas-Stimming 

Lora Digital Receiver Analysis And Implementation

R. Ghanaatian; O. Afisiadis; M. Cotting; A. Burg 

Low-Power Design of Digital VLSI Circuits around the Point of First Failure

Design of LDPC Codes for the Unequal Power Two-User Gaussian Multiple Access Channel

A. Balatsoukas-Stimming; A. P. Liavas 

Design Techniques for High-Speed Multi-Level Viterbi Detectors and Trellis-Coded-Modulation Decoders

H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. 

A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing

R. Ghanaatian; A. Balatsoukas-Stimming; T. Muller; M. Meidlinger; G. Matz et al. 

A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture

C. Condo; P. Giard; F. Leduc-Primeau; G. Sarkis; W. Gross 

Fast Low-Complexity Decoders for Low-Rate Polar Codes

P. Giard; A. K. Balatsoukas Stimming; G. Sarkis; C. Thibeault; W. J. Gross 

A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI

R. Giterman; A. Fish; A. Burg; A. Teman 

Faulty Successive Cancellation Decoding of Polar Codes for the Binary Erasure Channel

A. Balatsoukas-Stimming; A. Burg 

An 800-MHz Mixed-V-T 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications

R. Giterman; A. Fish; N. Geuli; E. Mentovich; A. Burg et al. 

Wireless Communication and Security Issues for Cyber-Physical Systems and the Internet-of-Things

A. Burg; A. Chattopadhyay; K-Y. Lam 

Fast-SSC-Flip Decoding of Polar Codes

P. Giard; A. Burg 

Design and Implementation of a Neural Network Aided Self Interference Cancellation Scheme for Full-Duplex Radios

Y. Kurzo; A. Burg; A. Balatsoukas-Stimming 

Non-Linear Digital Self-Interference Cancellation for In-Band Full-Duplex Radios Using Neural Networks

A. Balatsoukas-Stimming 

Majority Logic Synthesis

L. Amaru; E. Testa; M. Couceiro; O. Zografos; G. De Micheli et al. 

A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI

A. Bonetti; J. Constantin; A. S. Teman; A. P. Burg 

On the Tradeoff Between Accuracy and Complexity in Blind Detection of Polar Codes

P. Giard; A. Balatsoukas-Stimming; A. Burg 

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster

D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gurkaynak et al. 

Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes

A. Bonetti; N. A. Preyss; A. S. Teman; A. P. Burg 

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes

P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. Bonetti; C. Thibeault et al. 

An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems

J. Constantin; R. Houlmann; N. Preyss; N. Walenta; H. Zbinden et al. 

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters

A. Bonetti; A. S. Teman; P. Flatresse; A. P. Burg 

Blind detection of polar codes

P. Giard; A. K. Balatsoukas Stimming; A. P. Burg 

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

A. K. Balatsoukas Stimming; P. Giard; A. P. Burg 

High-Speed Wireline Link Design

Polar codes and APSK modulation – Just good friends

N. A. Preyss; P. Giard; A. K. Balatsoukas Stimming; A. P. Burg 

Cross-Layer Energy-Efficiency Optimization of Packet Based Wireless MIMO Communication Systems

C. Senning; G. Karakonstantis; A. Burg 

Wireless Channel Characterization in Burning Buildings Over 100-1000 MHz

A. C. M. Austin 

Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement

A. Teman; D. Rossi; P. Meinerzhagen; L. Benini; A. Burg 

Spatial Multiplexing of QPSK Signals With a Single Radio: Antenna Design and Over-the-Air Experiments

M. Yousefbeiki; A. C. M. Austin; J. R. Mosig; A. Burg; J. Perruisseau-Carrier 

Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs

N. Edri; P. Meinerzhagen; A. Teman; A. Burg; A. Fish 

A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications

L. Atias; A. Teman; R. Giterman; P. Meinerzhagen; A. Fish 

Synthesis of Dual Mode Logic

L. Moyal; I. Levi; A. Teman; A. Fish 

An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs

S. Brenna; A. Bonetti; A. Bonfanti; A. Lacaita 

Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65 nm CMOS

O. Andersson; B. Mohammadi; P. Meinerzhagen; A. Burg; J. N. Rodrigues 

Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications

R. Giterman; A. Teman; P. Meinerzhagen; L. Atias; A. Burg et al. 

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing

D. Rossi; A. Pullini; I. Loi; M. Gautschi; F. K. Gürkaynak et al. 

Digital Predistortion of Power Amplifier Non-Linearities for Full-Duplex Transceivers

A. Austin; A. K. Balatsoukas Stimming; A. Burg 

DynOR: A 32-bit Microprocessor in 28 nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment

J. H-F. Constantin; A. Bonetti; A. S. Teman; T. C. Müller; L. F. Schmid et al. 

Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices

L. G. Duch; P. Garcia del Valle; S. Ganapathy; A. P. Burg; D. Atienza Alonso 

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

J. Constantin; A. Burg; Z. Wang; A. Chattopadhyay; G. Karakonstantis 

Hardware Decoders for Polar Codes: An Overview

P. Giard; G. Sarkis; A. Balatsoukas-Stinning; Y. Fan; C-Y. Tsui et al. 

A 4.1 pJ/b 25.6 Gb/s 4-PAM Reduced-State Sliding-Block Viterbi Detector in 14 nm CMOS

H. Yueksel; M. Braendli; A. Burg; G. Cherubini; R. D. Cideciyan et al. 

Partitioned Successive-Cancellation List Decoding Of Polar Codes

S. A. Hashemi; A. Balatsoukas-Stimming; P. Giard; C. Thibeault; W. J. Gross 

Approximate Computing for Unreliable Silicon

A. P. Burg 

Statistical Fault Injection for Impact-Evaluation of Timing Errors on Application Performance

J. H-F. Constantin; Z. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg 

Sliding Window Spectrum Sensing for Full-Duplex Cognitive Radios with Low Access-Latency

O. Afisiadis; A. C. M. Austin; A. K. Balatsoukas Stimming; A. Burg 

A Multi-Gbps Unrolled Hardware List Decoder Systematic Polar Code

P. Giard; A. K. Balatsoukas Stimming; T. C. Müller; A. P. Burg; C. Thibeault et al. 

A Low-Power Correlator for Wakeup Receivers with Algorithm Pruning through Early Termination

R. Ghanaatian Jahromi; P. Whatmough; J. H-F. Constantin; A. S. Teman; A. P. Burg 

High-Speed Link With Trellis-Coded Modulation and Reed Solomon Coding

H. Yueksel; G. Cherubini; R. D. Cideciyan; S. Furrer; A. Burg et al. 

A Process Compensated Gain Cell Embedded-DRAM for Ultra-Low-Power Variation-Aware Design

R. Giterman; A. Teman; P. Meinerzhagen; A. Fish; A. Burg 

Microarchitectural Low-Power Design Techniques for Embedded Microprocessors

Modulation, Coding, and Receiver Design for Gigabit mmWave Communication

Hardware implementation aspects of polar decoders and ultra high-speed LDPC decoders

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

H. Kroell; S. Zwicky; B. Weber; C. Roth; D. Tschopp et al. 

Performance estimation for indoor wireless systems using FDTD method

A. Austin 

A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs

A. Teman; R. Visotsky 

Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs

M. Owaida; G. Falcao; J. Andrade; C. Antonopoulos; N. Bellas et al. 

Baseband and RF hardware impairments in full-duplex wireless systems: experimental characterisation and suppression

A. Balatsoukas-Stimming; A. Austin; P. Belanovic; A. Burg 

LLR-Based Successive Cancellation List Decoding of Polar Codes

A. Balatsoukas-Stimming; M. B. Parizi; A. Burg 

A 3.52 Gb/s mmWave Baseband with Delayed Decision Feedback Sequence Estimation in 40 nm

N. A. Preyss; C. C. S. D. Senning; A. P. Burg; W-C. Liu; C-Y. Liu et al. 

Fractionally Spaced Complex Sub-Nyquist Sampling for Multi-Gigabit 60 GHz Wireless Communication

N. A. Preyss; L. Koester; A. P. Burg 

Energy-Proportional Single-Carrier Frequency Domain Equalization for mmWave Wireless Communication

N. Preyss; S. Rodriguez Egea; A. Burg 

Fundamental Power Limits of SAR and ΔΣ Analog-to-Digital Converters

S. Brenna; L. Bettini; A. Bonetti; A. Bonfanti; A. Lacaita 

Approximate Computing With Unreliable Dynamic Memories

S. Ganapathy; A. S. Teman; R. Giterman; A. P. Burg; G. Karakonstantis 

Energy versus Data Integrity Trade-Offs in Embedded High-Density Logic Compatible Dynamic Memories

A. S. Teman; G. Karakonstantis; A. P. Burg; R. Giterman; P. A. Meinerzhagen 

Exploiting Dynamic Timing Margins in Microprocessors for Frequency-Over-Scaling with Instruction-Based Clock Adjustment

J. H-F. Constantin; L. Wang; G. Karakonstantis; A. Chattopadhyay; A. P. Burg 

An Overlap-Contention Free True-Single-Phase Clock Dual-Edge-Triggered Flip-Flop

A. Bonetti; A. S. Teman; A. P. Burg 

Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder

P. A. Meinerzhagen; A. Bonetti; G. Karakonstantis; C. Roth; F. K. Gürkaynak et al. 

Digital Synchronization for Symbol-spaced IEEE802.11ad Gigabit mmWave Systems

N. A. Preyss; A. Burg 

Mitigating the Impact of Faults in Unreliable Memories For Error-Resilient Applications

S. Ganapathy; G. Karakonstantis; A. S. Teman; A. P. Burg 

Concurrent Spectrum Sensing and Transmission for Cognitive Radio using Self-Interference Cancellation

A. Austin; O. Afisiadis; A. Balatsoukas-Stimming; A. Burg 

An FPGA-based Accelerator for Rapid Simulation of SC Decoding of Polar Codes

J. M. Wüthrich; A. K. Balatsoukas Stimming; A. P. Burg 

Circuits and Techniques for Dynamic Timing Monitoring in Microprocessors

A. Bonetti; J. H-F. Constantin; A. S. Teman; A. P. Burg 

Method and apparatus for low complexity spectral analysis of bio-signals

G. Karakonstantis; A. Sankaranarayanan; A. Burg; S. Murali; D. Atienza Alonso 

Power analysis and optimization of on-board processing for the EFM32 microprocessor

A. Gianarda 

Automated Performance Characterization of Dynamic Clock Adjustment Techniques on an OpenRISC ISS

B. Steinmann 

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology

F. Moradi; G. Panagopoulos; G. Karakonstantis; H. Farkhani; D. T. Wisland et al. 

Density Evolution for Min-Sum Decoding of LDPC Codes Under Unreliable Message Storage

A. Balatsoukas-Stimming; A. P. Burg 

A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory

H. Dagan; A. Shapira; A. Teman; A. Mordakhay; S. Jameson et al. 

A Lattice Reduction-Aided MIMO Channel Equalizer in 90 nm CMOS Achieving 720 Mb/s

C. Senning; L. Bruderer; J. Hunziker; A. Burg 

A Fast and Versatile Quantum Key Distribution System with Hardware Key Distillation and Wavelength Multiplexing

N. Walenta; A. P. Burg; D. Caselunghe; J. H-F. Constantin; N. Gisin et al. 

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design

I. Kazi; P. Meinerzhagen; P-E. Gaillardon; D. Sacchetto; Y. Leblebici et al. 

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

A. Teman; P. Meinerzhagen; R. Giterman; A. Fish; A. Burg 

Hardware Architecture for List Successive Cancellation Decoding of Polar Codes

A. Balatsoukas-Stimming; A. J. Raymond; W. J. Gross; A. Burg 

Energy Efficiency through Significance-Based Computing

D. S. Nikolopoulos; H. Vandierendonck; N. Bellas; C. D. Antonopoulos; S. Lalis et al. 

A Wireless Body Sensor Network For Activity Monitoring With Low Transmission Overhead

R. Braojos Lopez; I. Beretta; J. H-F. Constantin; A. P. Burg; D. Atienza Alonso 

Cross Layer Energy-Efficiency Optimization For Cognitive Radio Transceivers

C. Senning; M. Mendicute; A. Burg 

Correlation Based Phase Noise Compensation in 60 GHz Wireless Systems

N. A. Preyss; R. Pantic; A. P. Burg 

Variability-Aware Design Space Exploration of Embedded Memories

S. Ganapathy; G. Karakonstantis; R. Canal; A. P. Burg 

True MIMO transmission using a single RF-chain and antenna: recent developments

M. Yousefbeiki; P. Belanovic; A. P. Burg; J. Perruisseau-Carrier 

Robust Asynchronous Indoor Localization Using Led Lighting

G. Kail; P. Maechler; N. Preyss; A. Burg 

A Quality-Scalable and Energy-Efficient Approach for Spectral Analysis of Heart Rate Variability

G. Karakonstantis; A. Sankaranarayanan; M. M. S. Aly; D. Atienza Alonso; A. P. Burg 

Dynamic stability and noise margins of SRAM arrays in nanoscaled technologies

A. Teman 

Enabling Complexity-Performance Trade-Offs for Successive Cancellation Decoding of Polar Codes

A. Balatsoukas-Stimming; G. Karakonstantis; A. P. Burg 

Single event upset mitigation in low power SRAM design

L. Atias; A. Teman; A. Fish 

4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes

R. Giterman; A. Teman; P. Meinerzhagen; A. Burg; A. Fish 

LLR-based Successive Cancellation List Decoding of Polar Codes

A. Balatsoukas-Stimming; M. Bastani Parizi; A. P. Burg 

Data Compression via Logic Synthesis

L. Amarù; P-E. Gaillardon; A. Burg; G. De Micheli 

Novel Approaches Toward Area- and Energy-Efficient Embedded Memories

Energy Efficient VLSI Circuits for MIMO-WLAN

Cross-Layer Inexact Design for Low-Power Applications

V. Camus; G. Karakonstantis; J. Schlachter; A. P. Burg; C. Enz 

Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams

L. Amarù; A. Balatsoukas Stimming; P-E. Gaillardon; A. Burg; G. De Micheli 

Ultra-Low Power Multicore Architecture For Parallel Biomedical Signal Processing

A. Y. Dogan; J. Constantin; A. Burg; D. Atienza Alonso 

Low Power Wake-up Receiver

L. F. Schmid 

Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform

E. A. Pignat 

RSS Range Estimation for Indoor Localization Using LED Lighting

J. Liu 

Impact of body biasing on the retention time of gain-cell memories

A. Burg; A. Teman; A. Fish; P. Meinerzhagen 

Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

P. A. Meinerzhagen; A. Teman; R. Giterman; A. P. Burg; A. Fish 

Efficient VLSI Implementation of Reduced-State Sequence Estimation for Wireless Communications

S. Zwicky; C. Benkeser; A. P. Burg; Q. Huang 

On Self-interference Suppression Methods for Low-complexity Full-duplex MIMO

A. Balatsoukas-Stimming; P. Belanovic; K. Alexandris; A. Burg 

A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write

I. Kazi; P. A. Meinerzhagen; P-E. J. M. Gaillardon; D. Sacchetto; A. P. Burg et al. 

Fast and Accurate BER Estimation Methodology for I/O Links based on Extreme Value Theory

A. Cevrero; N. Evmorfopoulos; C. Antoniadis; P. Ienne; Y. Leblebici et al. 

Synchronizing Code Execution on Ultra-Low-Power Embedded Multi-Channel Signal Analysis Platforms

A. Y. Dogan; R. Braojos Lopez; J. H-F. Constantin; G. Ansaloni; A. P. Burg et al. 

Block-Floating-Point Enhanced MMSE Filter Matrix Computation for MIMO-OFDM Communication Systems

C. C. S. D. Senning; A. P. Burg 

FireBird: PowerPC e200 Based SoC for High Temperature Operation

R. Cojbasic; Ö. Cogal; P. A. Meinerzhagen; C. C. S. D. Senning; C. J. Slater et al. 

A Parallelized Layered QC-LDPC Decoder for IEEE 802.11ad

A. Balatsoukas Stimming; N. Preyss; A. Cevrero; A. Burg; C. Roth 

Energy-Aware Processing Platform Exploration for Embedded Biosignal Analysis

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing

J. H-F. Constantin; A. Dogan; O. Andersson; P. A. Meinerzhagen; J. Rodrigues et al. 

Application-Specific Processor Design for Low-Complexity & Low-Power Embedded Systems

J. H-F. Constantin 

A Multipurpose Testbed for Full-Duplex Wireless Communications

P. Belanovic; A. Balatsoukas-Stimming; A. Burg 

Near- and Sub-Threshold Design for Ultra-Low-Power Embedded Systems

A. P. Burg 

VLSI Design of Approximate Message Passing for Signal Restoration and Compressive Sensing

P. Maechler; C. Studer; D. Bellasi; A. Maleki; A. P. Burg et al. 

Analysis and VLSI Implementation of EWA Rendering for Real-Time HD Video Applications

P. Greisen; M. Schaffner; S. Heinzle; M. Runo; A. Smolic et al. 

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

G. Karakonstantis; D. Mohapatra; K. Roy 

Distributed static linear Gaussian models using consensus

P. Belanovic; S. Valcarcel Macua; S. Zazo 

Low-power processor architecture exploration for online biomedical signal analysis

A. Y. Dogan; J. H-F. Constantin; D. Atienza Alonso; A. P. Burg; L. Benini 

Replica Bit-Line Technique for Embedded Multilevel Gain-Cell DRAM

M. U. Khalid; P. A. Meinerzhagen; A. P. Burg 

Successive Interference Cancellation for 3G Downlink: Algorithm and VLSI Architecture

S. Belfanti; C. Benkeser; K. Badawi; Q. Huang; A. P. Burg 

Review and Classification of Gain Cell eDRAM Implementations

A. Teman; P. A. Meinerzhagen; A. P. Burg; A. Fish 

Design of Energy Efficient and Dependable Health Monitoring Systems under Unreliable Nanometer Technologies

M. M. S. Aly; G. Karakonstantis; D. Atienza Alonso; A. P. Burg 

Layered Detection and Decoding in MIMO Wireless Systems

N. A. Preyss; C. Studer; A. P. Burg 

Multi-Core Architecture Design for Ultra-Low-Power Wearable Health Monitoring Systems

A. Y. Dogan; J. H-F. Constantin; M. Ruggiero; A. P. Burg; D. Atienza Alonso 

A 2.78 mm2 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

F. Borlenghi; E. M. Witte; G. Ascheid; H. Meyr; A. P. Burg 

Low-complexity Frequency Synchronization for GSM Systems: Algorithms and Implementation

H. Kröll; S. Zwicky; C. Benkeser; Q. Huang; A. P. Burg 

TamaRISC-CS: An Ultra-Low-Power Application-Specific Processor for Compressed Sensing

J. H-F. Constantin; A. Y. Dogan; O. Andersson; P. A. Meinerzhagen; J. N. Rodrigues et al. 

Data Mapping for Unreliable Memories

C. Roth; C. Benkeser; C. Studer; G. Karakonstantis; A. P. Burg 

On the Exploitation of the Inherent Error Resilience of Wireless Systems under Unreliable Silicon

G. Karakonstantis; C. Roth; C. Benkeser; A. Burg 

Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture

J. H-F. Constantin; A. P. Burg; F. K. Gurkaynak 

A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS

P. A. Meinerzhagen; O. Andersson; B. Mohammadi; Y. Sherazi; A. P. Burg et al. 

Shortening design time through multiplatform simulations with a portable OpenCL golden-model: the LDPC decoder case

G. Falcao Fernandes; D. Novo Bruna; M. Purnaprajna; N. Bellas; C. Antonopoulos et al. 

Low Complexity Spectral Analysis of Heart-Rate-Variability through a Wavelet Based FFT

G. Karakonstantis; A. Sankaranarayanan; A. P. Burg 

A Sub-VT 2T Gain-Cell Memory for Biomedical Applications

P. A. Meinerzhagen; A. Teman; A. Mordakhay; A. P. Burg; A. Fish 

Two-Port Low-Power Gain-Cell Storage Array: Voltage Scaling and Retention Time

R. Iqbal; P. A. Meinerzhagen; A. P. Burg 

VLSI Implementation of Hard- and Soft-Output Sphere Decoding for Wide-Band MIMO Systems

C. Studer; M. Wenk; A. Burg 

Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture

J. H-F. Constantin; A. P. Burg; F. K. Gurkaynak 

Standard-Cell Based Memories (SCMs): from Sub-VT to Error-Resilient Systems

P. A. Meinerzhagen; J. N. Rodrigues; A. P. Burg 

1 Mbps coherent one-way QKD with dense wavelength division multiplexing and hardware key distillation

N. Walenta; A. P. Burg; J. H-F. Constantin; N. Gisin; O. Guinnard et al. 

Building a visible light communication system

C. Iliopoulos 

Benchmarking of standard-cell based memories in the sub-VT domain in 65-nm CMOS technology

P. A. Meinerzhagen; S. M. Y. Sherazi; A. P. Burg; J. N. Rodrigues 

An FPGA-based processing pipeline for high definition stereo video

P. Greisen; S. Heinzle; M. Gross; A. P. Burg 

Significance Driven Computation on Next-Generation Unreliable Platforms

G. Karakonstantis; N. Bellas; C. Antonopoulos; G. Tziantzioulis; V. Gupta et al. 

Synthesis strategies for sub-VT systems

P. A. Meinerzhagen; O. Andersson; Y. Sherazi; A. P. Burg; J. Rodrigues 

Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders

C. Roth; A. Cevrero; C. Studer; Y. Leblebici; A. Burg 

Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing

A. Y. Dogan; D. Atienza Alonso; A. P. Burg; I. Loi; L. Benini 

A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS Soft-Input Soft-Output Sphere Decoder

F. Borlenghi; E. M. Witte; G. Ascheid; H. Meyr; A. P. Burg 

System-level implications of residual transmit-RF impairments in MIMO systems

C. Studer; M. Wenk; A. P. Burg 

Computational stereo camera system with programmable control loop

S. Heinzle; P. Greisen; D. Gallup; C. Chen; D. Saner et al. 

Design and failure analysis of logic-compatible multilevel gain-cell-based DRAM for fault-tolerant VLSI systems

P. A. Meinerzhagen; O. Andiç; J. Treichler; A. P. Burg 

Random Sampling ADC for Sparse Spectrum Sensing

P. Maechler; N. Felber; A. P. Burg 

Simulation and Emulation of MIMO Wireless Baseband Transceivers

P. Greisen; S. Haene; A. Burg 

MIMO transmission with residual transmit-RF impairments

C. Studer; M. Wenk; A. Burg 

The effect of unreliable LLR storage on the performance of MIMO-BICM

C. Novak; C. Studer; A. Burg; G. Matz 

Area- and throughput-optimized VLSI architecture of sphere decoding

M. Wenk; L. Bruderer; A. Burg; C. Studer 

Towards generic low-power area-efficient standard cell based memory architectures

P. A. Meinerzhagen; C. Roth; A. P. Burg 

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

C. Roth; P. A. Meinerzhagen; C. Studer; A. P. Burg 

Systolic-array based regularized QR-decomposition for IEEE 802.11n compliant soft-MMSE detection

C. Senning; A. Staudacher; A. Burg 

VLSI Implementation of a Low-Complexity LLL Lattice Reduction Algorithm for MIMO Detection

L. Bruderer; C. Studer; M. Wenk; D. Seethaler; A. Burg 

Low-complexity Seysen’s algorithm based lattice reduction-aided MIMO detection for hardware implementations

L. Bruderer; C. Senning; A. Burg 

Matching pursuit: Evaluation and implementatio for LTE channel estimation

P. Maechler; P. Greisen; N. Felber; A. Burg 

Design and Optimization of an HSDPA Turbo Decoder ASIC

C. Benkeser; A. Burg; T. Cupaiuolo; Q. Huang 

Implementation of a 2×2 MIMO-OFDM receiver on an application specific processor

S. Eberli; A. P. Burg; W. Fichtner 

A 4-Stream 802.11n Baseband Transceiver in 0.13 mu m CMOS

A. Burg; S. Haene; M. Borgmann; D. Baum; T. Thaler et al. 

A real-time 4-stream MIMO-OFDM transceiver: System design, FPGA implementation, and characterization

S. Haene; D. Perels; A. Burg 

Soft-output sphere decoding: Algorithms and VLSI implementation

C. Studer; A. Burg; H. Boelcskei 

Hardware-efficient steering matrix computation architecture for MIMO communication systems

C. Senning; C. Studer; P. Luethi; W. Fichtner 

Configurable High-Throughput Decoder Architecture for Quasi-Cyclic LDPC Codes

C. Studer; N. A. Preyss; C. Roth; A. Burg 

A 58mW 1.2 mm 2 HSDPA Turbo Decoder ASIC in 0.13 μm CMOS

C. Benkeser; A. Burg; T. Cupaiuolo; Q. Huang 

FFT processor for OFDM channel estimation

S. Haene; A. Burg; R. Luethi; N. Felber; W. Fichtner 

VLSI implementation of a high-speed iterative sorted MMSE QR decomposition

P. Luethi; A. Burg; S. Haene; D. Perels; N. Felber et al. 

An IEEE 802.11a baseband receiver implementation on an application specific processor

S. Eberli; A. Burg; T. Boesch; W. Fichtner 

Regularized frequency domain equalization algorithm and its VLSI implementation

A. Burg; S. Haene; W. Fichtner; M. Rupp 

VLSI implementation of a lattice-reduction algorithm for multi-antenna broadcast precoding

A. Burg; D. Seethaler; G. Matz 

VLSI implementation of the list sphere algorithm

M. Wenk; A. Burg; M. Zellweger; C. Studer; W. Fichtner 

A frame-start detector for a 4×4 MIMO-OFDM system

D. Perels; S. Haene; A. Burg; P. Luethi; N. Felber et al. 

K-Best MIMO detection VLSI architectures achieving up to 424 mbps

M. Wenk; M. Zellweger; A. Burg; N. Felber; W. Fichtner 

Silicon implementation of an MMSE-based soft demapper for MIMO-BICM

S. Haene; A. Burg; D. Perels; P. Luethi; N. Felber et al. 

Advanced receiver algorithms for MIMO wireless communications

A. Burg; M. Borgmann; M. Wenk; C. Studer; H. Boelcskei 

A unification of ML-optimal tree-search decoders

C. Studer; A. Burg; W. Fichtner 

Algorithm and VLSI architecture for linear MMSE detection in MIMO-OFDM systems

A. Burg; S. Haene; D. Perels; P. Luethi; N. Felber et al. 

Soft-output sphere decoding: Performanceand implementation aspects

C. Studer; M. Wenk; A. Burg; H. Bolsckei 

VLSI implementation of MIMO detection using the sphere decoding algorithm

M. Borgmann; M. Wenk; M. Zellweger; W. Fichtner; H. Bolcskei et al. 

Interpolation-based QR decomposition in MIMO-OFDM systems

M. Borgmann; H. Bolcskei; J. Hansen; A. Burg; D. Cescato 

ASIC implementation of a MIMO-OFDM transceiver for 192 Mbps WLANs

S. Haene; P. Luethi; A. Burg; N. Felber; W. Fichtner et al. 

FPGA implementation of Viterbi decoders for MIMO-BICM

S. Haene; A. Burg; D. Perels; P. Luethi; N. Felber et al. 

Receiver design for multi-antenna wireless communications

S. Haene; D. Perels; P. Luethi; N. Felber; W. Fichtner et al. 

Low complexity frequency domain equalization of MIMO channels with applications to MIMO-CDMA systems

M. Rupp; S. Haene; D. Perels; N. Felber; W. Fichtner et al. 

Performance of MIMO-extended UMTS-FDD downlink comparing space-time RAKE and linear equalizer

M. Rupp; D. Perels; S. Haene; N. Felber; W. Fichtner et al. 

VLSI implementation of the sphere decoding algorithm

M. Wenk; M. Zellweger; M. Wegmueller; N. Felber; W. Fichtner et al. 

Rapid prototyping for wireless designs: the five-ones approach

A. Burg; E. Beck; M. Rupp 

Practical low complexity linear equalization for MIMO-CDMA systems

M. Rupp; N. Felber; W. Fichtner; A. Burg 

Variable delay ripple carry adder with carry chain interrupt detection

F. Gurkaynak; H. Kaeslin; W. Fichtner; A. Burg 

Efficient ASIC implementation of a real-time depth mapping stereo vision system

S. Moser; O. Isler; F. Gurkaynak; A. Burg; N. Felber et al. 

A 50 MBPS 4×4 maximum likelihood decoder for multiple-input multiple-output systems with QPSK modulation

N. Felber; W. Fichtner; A. Burg 

Programmable code processor for software defined radio

R. Bischoff; J. Biveroni; M. Bruehwiler; A. Burg; N. Felber et al. 

An ASIC implementation of adaptive arithmetic coding

M. Sans; A. Burg; W. Fichtner; G. Acunto 

Rapid prototyping design of a 4×4 BLAST-over-UMTS system

A. Burg; M. Rupp; E. Beck; S. Das; M. Guillaud 

From basic concept to real-time implementation: Prototyping WCDMA downlink receiver algorithms – A case study

A. Burg; L. Mailaender; B. Haller; M. Rupp; E. Beck et al. 

A 3D-DCT real-time video compression system for low complexity single-chip VLSI implementation

A. P. Burg; R. Keller; J. Wassner; N. Felber; W. Fichtner