Introducing the first open-source RISC-V-based FS-validated simulation models with a complete and replicable methodology
Full-System simulation is essential for performance evaluation of complete systems that execute complex applications on a complete software stack consisting of an operating system and user applications. Nevertheless, they require careful fine-tuning against real hardware to obtain reliable performance statistics, which can become tedious, error-prone, and time-consuming with typical trial-and-error approaches.
A team of our researchers proposes a novel, streamlined, component-level calibration methodology to address these shortcomings to validate FS simulation models. The methodology significantly accelerates the validation process without sacrificing accuracy.
The methodology is Instruction Set Architecture (ISA)-agnostic, and can tackle hardware specifications at different levels of detail. Our team demonstrated its effectiveness by validating FS models against both open-hardware and IP-protected (closed hardware) RISC-V silicon, achieving a mean error of 19-23% for the SPEC CPU2017 suite in the two cases.
Congratulations to Karan Pathak, Joshua Klein, Giovanni Ansaloni, Said Hamdioui, Georgi Gaydadjiev, Marina Zapater and David Atienza for this groundbreaking work, which has been published in the Association for Computing Machinery’s Transactions on Embedded Computing Systems.
Towards Accurate RISC-V Full System Simulation via Component-level Calibration
Karan Pathak, Joshua Klein, Giovanni Ansaloni, Said Hamdioui, Georgi Gaydadjiev, Marina Zapater, David Atienza
ACM Transactions on Embedded Computing Systems
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Full system simulation and design