In all ICP tools available at CMi zone2, the backside of the processed wafer should be electrically conductive enough to be gripped during the process, or clamped, by the Electro-Static Chuck (ESC) it sits onto. This ESC is an electrode connected to a DC power supply and that is buried within a dielectric material.
To properly clamp the wafer, the DC power supply creates equal charges but of opposite signs across the dielectric to the substrate, building up a capacitor equivalent scheme, whose top electrode would be the wafer itself.
A few micrometers of oxide for example are negligible. But bulk dielectric materials cannot be easily clamped. To help if needed, one can deposit a ~100 nm layer of e.g. Al, W, Cr, Ti, aSi… on the backside of the wafer to improve its electrical conductivity (keeping in mind the material compatibility of the tools !).
During the etching process, the small vicinity space between the wafer and the ESC is filled with Helium gas that acts as thermal conductor. It allows the wafer to evacuate the heat accumulated during process down to the bottom part of the tool the ESC is in contact with. For best cooling capability, the Helium gas must remain confined below the wafer, so the backside of the wafers must be electrically conductive enough for good clamping, but also must be particularly clean ! Any small particle/dust or feature can locally affect thermal stability of the process.
Conclusion: wafer front side only is just not enough! Wafer backside preparation and inspection is key for successful ICP etching !
Effective thermal stability of the sample is one of the key parameters for dry etching.
At wafer scale, direct thermal contact between wafer and ESC is ensured with confined Helium gas back pressure.
If a chip is to be processed and placed on a carrier wafer, thermal contact must also be ensured: QS135 wax (quick-stick) should be used for good thermal conductivity between the carrier wafer and the chip.
See “Quick-Stick” guidelines on restricted area.
Depending on the needed final quality of the sample, (large) through openings can be made in two different ways.
1. With a backside stop layer
Some fabrication requires etching all the way through a wafer. Some care must be taken for proper result and to avoid putting the etching tool at risk.
An etch stop layer should always be present in order to avoid:
1) Helium gas backpressure release that interlocks the etch process
2) Exposing the ESC to the active etch process and its energetic ions.
If no topography on backside, this stop layer can be made of a 2 to 5 um layer of Al or of Parylene. This latest is the only choice if there’s topography on backside.
This etch stop layer is then removed by wet etching or by O2 plasma to free the structures.
2. With partial etch and backside grinding
Having an etched-through wafer is also possible without a backside etch stop layer: it is done with frontside partial etch of the wafer and then backside grinding of the remaining material.
When dry etching through a wafer, stress will occur on the backside stop layer due to the Helium gas back pressure. For large >mm structures, the stop layer may fail. To improve the result yield, and also to take into account ARDE and macro-loading effects, the etched design must be adapted: shape the final large open structure not by etching its whole area, but by etching only its periphery with a cut-out width of 500um (for limited final aspect ratio). The inside unwanted material will be gone detached together with the removal of the backside etch stop layer as final step of the process.
After a dry process where energetic ions are involved, the photoresist mask can be modified to a level where a thin crust can form as very top layer. It is created when ions have enough energy to turn the photoresist’s chemistry into higher cross-linking levels. The hard top layer on the surface makes the resist difficult to remove with wet cleaning. For such cases, it is recommended to first perform a short in time but high in power step of oxygen plasma, in order to crack through this hard top layer, and helping for most efficient subsequent wet removal of the resist.
After dry Aluminum etch with Cl2 based chemistry, some chlorine will remain trapped at edges of the features and on resist surface. HCl creation will locally initiate as soon as the sample is in contact with the moisture present in the air, and corrosion of the Aluminum layer will expand.
To avoid the slow corrosion of Aluminum with time, it is advised to first heavily rinse the sample in a high volume of DI water as soon as the wafer is collected. This will dilute and rinse away the Chlorine that is present on surfaces of the sample. This does not fully remove the whole amount of Chlorine, but allows some time for quick inspection and metrology before the photoresist mask is fully removed. Best is to remove the photoresist mask as soon as possible.
Another possibility is to substitute the adsorbed Chlorine elements by Fluorine inside the ICP tool directly, and before the sample is put in contact with moisture when returned at ambient atmosphere. In-situ CF4/O2 process is available on Cobra etcher for this purpose. This process has the benefit of also removing the PR mask, but the inconvenient of slowly etching SiO2 or SiN layers. So not always usable.
During KOH wet etching of Silicon, potassium salt residues are released as by-product of the reaction and remain on the etched zones of the sample. Even if in rare cases this K-salt can have no impact on the devices, it is most of the time needed to remove it in order to recover a fully clean surface and a contamination-free sample.
To do so, a neutralization step is done by immersing the sample for 2 hours in concentrated HCl. In some cases, diluted HCl + H2O2 can be used as a more aggressive exothermic neutralization.
