With the introduction of SPAD detectors integrated in CMOS technology, highly sensitive miniaturized cameras became possible. SPAD detectors were used from their introduction for the realization of ultra-high speed CMOS cameras. They enable extremely small integration times with limited power dissipation. The trade-off between dynamic range and speed can be managed through the use of reconfigurable detection architectures. In addition to conventional high-speed imaging, ultra-high speed cameras also enable real-time imaging in computationally demanding applications by taking advantage of fast and parallel data processing.
Due to their all-digital nature SPAD based CMOS image sensors are ideally suited to create high-speed camera systems. Indeed, SPAD arrays were used early on as high frame-rate cameras to observe fast phenomena. An instrument where fast cameras are needed is the disdrometer, a device used to analyze the drop size distribution and velocity of precipitation in order to distinguish between rain, hail, snow and more. The development of the first SwissSPAD sensor was prompted by the quest for a better disdrometer.
SwissSPAD1 is a 512×128 pixel SPAD sensor, where each pixel has a 1-bit memory element and a gating circuit allowing integration times as low as 5ns. The sensor is connected to an FPGA with an aggregate bandwidth of 12.8 GBps distributed over 128 connections. The FPGA operates the sensor, controlling the gating and integrating images, in response to requests from a computer.
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| SwissSPAD1 schematic
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SwissSPAD1 micrograph
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Spartan 6 motherboard for SwissSPAD1
The SwissSPAD1 camera system was initially based on a dual FPGA motherboard using Virtex 4 FPGAs (Broaddown4 by Enterpoint Ltd., https://www.enterpoint.co.uk/products/virtex-4-development-boards/broaddown-4/) before using our own smaller (8cm x 16cm) motherboard with a single Spartan 6 FPGA. The system has been used, among others, to generate random numbers, for super resolution microscopy and in single plane illumination fluorescence correlation spectroscopy (SPIM-FCS).
SwissSPAD1 was designed such, that two sensors could be placed side-by-side to double the resolution to 256 x 512 pixels with a minimal gap. Unfortunately, due to fabrication issues leading to low yield this could never be tested.
SwissSPAD2 was designed in a smaller fabrication process with 512×512 pixels and using 256 data lines for communication. Otherwise the architecture is comparable to SwissSPAD1 with each pixel containing a 1-bit memory and gating circuitry. It can achieve a frame rate up to 97,700 binary frames per second, or 382 8-bit frames per second. Time-resolved imaging can be performed with an integrated in-pixel gate that can shift by steps of 18 ps with respect to a laser pulse. Its camera module is based on a motherboard with a Xilinx Kintex-7 FPGA, which can currently access a sub-array with 472×256 pixels. The development of a new camera module based on two motherboards that can access the entire 512×512 array is ongoing.
SwissSPAD2 employs a SPAD design that achieves one of the highest sensitivity (50% PDP at 520 nm) and lowest dark count rate (0.26 cps/µm2) combinations among SPADs designed in standard CMOS process technologies. Its 10.5% native fill factor is expected to be improved with microlenses to more than 50%, which will make the camera more suitable for applications requiring detection of weak signals, such as fluorescence lifetime imaging microscopy (FLIM).
So far, SwissSPAD2 was used in widefield FLIM, which is a typically computationally expensive biomedical application. The ultimate goal in this research is to perform FLIM in real time (>1 fps). Aside from stringent sensitivity requirements, fast and continuous readout is of key importance to achieve this goal. For continuous readout, the processing speed of the raw data into lifetime needs to keep up with the readout speed. The current stage of the research is focused on FPGA-based parallel lifetime calculation towards achieving the real time goal.
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| Photomicrograph | Camera module of SwissSPAD2 |
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| 4-bit images of a rotating fan with a high-speed SPAD camera at | |
| (a) 0.6 kfp |
(b) 6.1 kfps |
Applications
- Scientific imaging
- In-vivo cortical scanning
- Fast interface devices
- Security monitoring
- Games
- Communications
Relevant publications
A.C. Ulku, C. Bruschini, X. Michalet, S. Weiss and E. Charbon, “A 512×512 SPAD image sensor with built-in gating for phasor based real-time siFLIM”, in Int. Image Sensor Workshop, Hiroshima, 2017.
I. M. Antolovic*, S. Burri*, R. Hoebe, Y. Maruyama, C. Bruschini and E. Charbon, “Photon-Counting Arrays for Time-Resolved Imaging”, in Sensors, vol. 16, num. 7, 2016. http://www.mdpi.com/1424-8220/16/7/1005
I. M. Antolovic*, S. Burri*, C. Bruschini, R. Hoebe and E. Charbon, “Nonuniformity Analysis of a 65-kpixel CMOS SPAD Imager”, in IEEE Transactions on Electron Devices, vol. 63, DOI: 10.1109/TED.2015.2458295, 2015. http://ieeexplore.ieee.org/document/7177073/
J. Buchholz, J.W. Krieger, S. Burri, C. Bruschini, E. Charbon, U. Kebschull and J. Langowski, “Single photon avalanche diode arrays for single plane illumination fluorescence correlation spectroscopy”, Focus On Microscopy Conference, Sidney, Australia, April 13-16, 2014.
S. Burri, Y. Maruyama, X. Michalet, F. Regazzoni, C. Bruschini and E. Charbon, “Architecture and applications of a high resolution gated SPAD image sensor”, Opt. Exp., vol. 22, no.14, pp. 17573-17589, 2014. https://www.osapublishing.org/oe/abstract.cfm?URI=oe-22-14-17573
S. Burri, D. Stucki, Y. Maruyama, C. Bruschini, E. Charbon and F. Regazzoni, “Jailbreak Imagers: Transforming a Single-Photon Image Sensor into a True Random Number Generator”, International Image Sensor Workshop, Utah, USA, June 12-16, 2013.
F. E. Powolny, S. Burri, C. Bruschini, X. Michalet, F. Regazzoni, and E. Charbon, “Comparison of Two Cameras based on Single Photon Avalanche Diodes (SPADs) for Fluorescence Lifetime Imaging Application with Picosecond Resolution”, International Image Sensor Workshop, Utah, USA, June 12-16, 2013.
E. Charbon, Will CMOS imagers ever need ultra-high speed?, in IEEE International Conference on Solid-State and Integrated-Circuit Technology, Beijing, 2004.