Available student projects at LAP

Updated: 05-05-2026

Open-Source Work on Dynamic High-level Synthesis Compiler Targeting FPGAs

Supervisor: Andrea Guerrieri ([email protected])

Dynamic high-level synthesis (DHLS) is the process of turning high-level source code into synchronous dynamically scheduled circuits. We offer opportunities to work on an open-source DHLS compiler called Dynamatic that is based on the MLIR compiler ecosystem and which generates synthesizable RTL that targets FPGA architectures from C/C++ code. Projects can revolve around writing compiler passes that transform our intermediate representation (IR) at some level of our progressive lowering pipeline. These go from close-to-source high-level analysis steps (e.g., memory dependence analysis, loop transformations) down to dataflow circuit-level transformations (e.g., buffer placement, bit-width optimisation). We also have open lines of work in the infrastructure surrounding the core compiler, be it debugging, visualisation, or benchmarking tools. Regardless of the exact line of work, as an open-source project we value good software design, solid development practices, and want to make any student contribution a permanent part of Dynamatic’s codebase. If you would like to discuss potential directions, please reach out with your resume/transcript and any specific interest you may have.

Accelerate FPGA Implementation Time

Supervisor: Andrea Guerrieri ([email protected])

FPGAs are powerful devices from embedded applications to data centres. However, developing with FPGAs requires hardware design skills and a long implementation time. High-level synthesis covers the gap in creating hardware design from C/C++ code. However, the time required to generate a bitstream configuration to download to the FPGA is still very long. This project aims to accelerate the FPGA implementation design from several minutes to a few seconds.

Postquantum Cryptography Core Using High-Level Synthesis

Supervisor: Andrea Guerrieri ([email protected])

In 2016, the American National Institute of Standards and Technology (NIST) started a contest to qualify a set of post-quantum cryptography standards. High-level synthesis produces HDL code for FPGAs out of C/C++ in an automatic way, bridging the gap from algorithm to hardware design. However, the quality of results could be suboptimal compared to RTL-based (Register Transfer Level) designs. This project aims to explore and improve the QoR of the post-quantum cryptography hardware using HLS. 

Low-Level Optimization of Dynamically Scheduled Circuits

Supervisor: Rouzbeh Pirayadi ([email protected])

Dynamic High-Level Synthesis (DHLS) transforms high-level source code into synchronous, dynamically scheduled circuits, offering a flexible alternative to traditional static scheduling. While significant research focuses on high-level compiler IR transformations, there is a distinct opportunity to improve performance by targeting the lower levels of the hardware implementation flow. This project explores optimizations that occur after the core compiler has generated its output, specifically focusing on the transition from RTL to a physical FPGA implementation to bridge the abstraction gap between the DHLS compiler’s intermediate representation and the final hardware bitstream. By operating within the Vivado environment, the student will investigate adjustments that can be made during and after the logic synthesis and place-and-route phases, refining the produced circuit based on real physical constraints, such as routing delays and logic congestion, which are invisible at the high-level compiler stage.

Toward Coarse-Grained Field Programmable Gate Arrays

Supervisor: Louis Coulon ([email protected])

Reconfigurable computing systems are ideal candidates to fulfil the  growing need for hardware specialization. They enable the mapping of  applications to efficient dedicated digital circuits which can be  implemented on generic computing fabrics, thus improving both  performance and energy efficiency while still being capable of  supporting virtually any application. In practice, the only reconfigurable computing system available commercially today is the  FPGA, recently adopted as a computing device in data centres and targeted  by all high-level synthesis compilers to ease its programming. However,  in data centre setting, there is a striking mismatch between the FPGA  programmable fabric and the computing needs of applications: these  generally perform word-level computations, while FPGAs allow bit-level  reconfigurability and provide bit-level abstractions. In this project,  we study a coarser granularity version of FPGAs and evaluate its  performance as a word-level reconfigurable computing fabric. We offer  opportunities to work on new compiler optimisations targeting this new  category of processors, new architectural ideas, and the physical  implementation and modelling of such processors.

Optimizing place and route for high frequency task parallel FPGA accelerators

Supervisor: Mohamed Shahawy ([email protected])

SOC-graphical configurator as VS-code plugin

Supervisor: Theo Kluter (ties.kluter@epfl.ch)