Full Custom Digital Design

Design of a Replica Circuit with Body-Bias Tunability for Variation Tracking and Compensation in CMOS 28nm FD-SOI

Type: Master project for one student or semester project for two students

A voltage guarband on the supply is conventionally used to account for temperature variations, droop events and aging effect. However, the considered guardband is generally overdesigned, resulting in an unrequired large power overhead. Replica circuits are used to track the delay change of the critical path due to variations and apply the required guardband whenever it is required. An alternative to supply voltage compensation is body-biasing that allows for a very accurate delay compensation. The goal of this project is to investigate how the critical path is affected by variations and designing a replica circuit that is able to accurately track the delay changes and compensate them through body-bias. The task of this project are the following:
  • Investigation of the standard-cell library across variations
  • Design of a replica circuit with programmable delay line and time-to-digital converter
  • Performance analysis of the replica delay tracking
  • Analysis of delay compensation through body-bias in CMOS 28nm FD-SOI
Work distribution: 10% literature review, 20% library investigation, 30% circuit design, 20% performance analysis, 20% verification and simulations
Areas: library investigation, low-power digital circuits, variations tracking and compensation, body-bias in FD-SOI

Design of a synthesizeable digital frequency locked loop (FLL)

Semester Project for 2 OR Master Project

Description: Modern system on chips designs integrate multiple IP blocks to implement all kinds of functionality. Each of these blocks may have been designed for a different nominal clock frequency which has to be supplied. An FLL can be used to derive a fast internal clock from a single slow but precise reference clock generated by an external crystal circuit.

The goal of this project is to implement a programmable FLL, capable of generating custom frequencies over a wide range, utilizing body biasing as a knob to fine tune the integrated oscillating circuit. The final circuit operation is to be verified across process corners and supply voltages.

Prerequisites: Knowledge of VHDL, Basic knowledge of analog simulation of digital cells (ideally Cadence Virtuoso)

Workload: 50% VHDL, 30% Digital cell design, 20% Simulation & Verification

Area: IC Design, Digital design, Mixed Signal, Clock domain crossing

Supervisor: Christoph Müller

Date added: 30-11-2016