Content Addressable Memory Implementation Using Gain-Cell Embedded DRAM
Description: Content-addressable memory (CAM) is a high-speed search engine that performs fully-parallel comparisons between input search data and a table of storage data in a single clock cycle. CAM has been widely used in applications requiring fast search operation including network routers, neural networks and image processing. However, the high search speed of CAM comes at the cost of large area and high power consumption. CAMs are usually implemented using Static Random Access Memory (SRAM) – based bitcells which require between 12-16 transistors per memory cell. Gain-Cell Embedded DRAM (GC-eDRAM) is a popular logic-compatible alternative to SRAM, offering up-to 2X higher density, two-ported operation and low power consumption. However, GC-eDRAM requires periodic refresh cycles to retain its data, which is set according to the worst-case data retention time under process, voltage, and temperature (PVT) variations.
In this project, we will analyze and design different GC-eDRAM – based structures for the implementation of CAMs. The designed memory cells will be compared to state-of-the-art CAM implementations in terms of area, power, and speed.
Areas: Circuit Design, Cadence Virtuoso
Supervisor: Robert Giterman, Christoph Thomas Muller
Data added: 07.06.2019
Efficient Neural Networks Accelerators Using Error-Tolerant Embedded DRAMs (2 Semester Projects / 1 Master Project)
Description: The growing size of convolutional neural networks (CNNs) requires large amounts of on-chip storage. The limited on-chip memory capacity often causes massive off-chip memory accesses and leads to very high system energy consumption. On-chip memories are usually implemented with Static Random Access Memory (SRAM), which often consume over 50% of the total chip area due to their inefficient size, and dominates system power due to its limited voltage scaling capabilitits. Gain-Cell Embedded DRAM (GC-eDRAM) is a logic-compatible alternative to SRAM, offering up-to 2X higher density, two-ported operation and low power consumption. However, GC-eDRAM requires periodic refresh cycles to retain its data, which is set according to the worst-case data retention time under process, voltage, and temperature (PVT) variations.
In this project, we will evaluate the benefits of using GC-eDRAM as the on-chip memory for CNNs, including analysis of refresh rate relaxation and its impact on CNNs accuracy, power, and bandwidth. The project can focus on two parts of the development stack; first on a Python-based CNN simulator for which an GC-eDRAM behavioral model has to be implemented, second on an FPGA/C-based emulation platform of GC-eDRAM for which a CNN needs to be implemented.
Areas:
Project 1: Python/C
Project 2: FPGA/C
Supervisor: Robert Giterman, Christoph Thomas Muller
Data added: 07.06.2019
Design of a Gain-Cell eDRAM for IoT
Topic:
- Gain-Cell eDRAMs are much more dense than conventional SRAMs
- Designing these very sensible circuits is almost an art…
Project Goals:
- Gain more knowledge about gain-cell eDRAMs
- Work on design improvements of the bitcell
- Design a complete gain-cell eDRAM
Areas: full-custom design (Virtuoso)
Supervisor: Andrea Bonetti
Modelling of Embedded DRAMs
Topic:
- Memory compilers are widely used to investigate/generate memory macros
- Model to predict performance of an embedded DRAM
Project Goals:
- Gain more knowledge about the design of a complete memory system
- Provide support with the simulation environment
- Improve the mathematical equations behind the model
Areas: full-custom design (Virtuoso), modeling, scripting
Supervisor: Andrea Bonetti
Application of Body-Bias to Gain-Cell Memories in CMOS 28nm FD-SOI
Type: Semester/Master project
- Design and simulation of a gain-cell memory to familiarize with the circuit
- Investigation on the performance of the gain cell with different body-bias settings
- Evaluating the design benefits and limitations of body-bias for an entire gain-cell array
- Design and validation of a gain-cell array with body-bias
Emulating an Embedded DRAM on FPGA
Topic:
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Project Goal: emulate the behaviour of an embedded DRAM on FPGA
- Gain basic knowledge on the data retention time in eDRAMs
- Design a VHDL representation of the eDRAM
- Analyze the behavior/impact of the memory within an application
Areas: FPGA, VHDL
Supervisor: Andrea Bonetti