Thermal Scanning Probe Lithography

Thermal scanning probe lithography (t-SPL) is an emerging technique for rapid prototyping at the nanometer scale. In t-SPL, a heated atomic force microscopy tip is used to pattern a temperature sensitive resist. The fine control over the indentation depth of the tip via an electrostatic potential between the tip and the substrate allows fabrication of grey scale patterns at high precision. These structures can then be transferred into SiOx or Si.

Working Principle

Using the NanoFrazor, a t-SPL tool commerically produced by Swisslitho AG thermal modification of polymer and non-polymeric substrates can be accomplished with nanometer precision at high-speed. In contrast to e-beam lithography, t-SPL can be applied on electron sensitive materials such as InAs nanowires. Another unique feature of NanoFrazor is it’s ability to scan surfaces during patterning. This allows for rapid prototyping.

The basic working principle of thermal patterning is visualized in Figure 1a and 1b. The NanoFrazor canilevers are equipped with two resistive heating elements as shown in Figure 1a). One heater is located above the tip and the second in one of the outer legs. The first heater is used to provide heat to the tip apex via thermal conductance, allowing precise modification of the substrate. The second heater serves as a height sensor which detects changes in the distance between the cantilever and the substrate. During scanning, the thermal height sensing allows fast detection of the patterned topography. More information on the working principle can be found here.

Figure 1b shows the thermal indentation of poly-phthalaldehyde (PPA), a self-amplified resist that decomposes upon exposure to heat (>300°C, ~10µs). By scanning the tip pixel-by-pixel over the surface a 3D topography can be obtained. Figure 1c shows a replica of the Rolex Learning Center at a size of 9.5×6.9µm in PPA, down to the wavy contours of the roof.

Pattern transfer

Patterns written into PPA can be transferred into silicon via a dedicated process developped in our lab in collaboration with SwissLitho AG as shown in Figure 2a and 2b. Figure 2c shows a SEM image of structures translated into silicon.

Nanoscale Modification of Supramolecular Glasses

Not only thermal-sensitive resists, but in fact, any material that responds to heat can, in principle, be thermally modified by t-SPL at the nanometer scale.

As an example, we modified a fluorescent supramolecular glass to fabricate nano- to microscale security features. This material changes its fluorescence emission wavelength upon heating due to structural changes at the molecular level, which can be observerd using a conventional fluorescence microscope. The results of these modifications can be seen in the below figures. The right figure displays an AFM topography of a modified surface, while the left figure is the results of scanning the surface with the flourescence microscope.



Fast turnaround fabrication of silicon point-contact quantum-dot transistors using combined thermal scanning probe lithography and laser writing

C. Rawlings; Y. K. Ryu; M. Rüegg; N. Lassaline; C. Schwemmer et al. 

Nanotechnology. 2018-10-12. DOI : 10.1088/1361-6528/aae3df.

Combination of thermal scanning probe lithography and ion etching to fabricate 3D silicon nanopatterns with extremely smooth surface

Y. Lisunova; J. Brugger 

Microelectronic Engineering. 2018-06-05. DOI : 10.1016/j.mee.2018.02.012.

Control of the interaction strength of photonic molecules by nanometer precise 3D fabrication

C. D. Rawlings; M. Zientek; M. Spieser; D. Urbonas; T. Stöferle et al. 

Scientific Reports. 2017. DOI : 10.1038/s41598-017-16496-x.

Nanopatterning of a Stimuli-Responsive Fluorescent Supramolecular Polymer by Thermal Scanning Probe Lithography

S. T. Zimmermann; D. W. H. Balkenende; A. Lavrenova; C. Weder; J. Brugger 

ACS Applied Materials and Interfaces. 2017. DOI : 10.1021/acsami.7b13672.

High-aspect ratio nanopatterning via combined thermal scanning probe lithography and dry etching

Y. Lisunova; M. Spieser; R. Juttin; F. Holzner; J. Brugger 

Microelectronic Engineering. 2017. DOI : 10.1016/j.mee.2017.04.006.