Main Publications

1992-1996 Research Report

Publications on the Applications of Neural Networks

• Fr�d�ric Aviolat, Daniel Cattani, and Thierry Cornu.
  Recognition of meteorological situations with neural networks. In Proceedings of the Third Biennial Joint Conference on Engineering systems Design & Analysis, ESDA'96 , Montpellier, July 1996. AMSE PD-Vol.79. Volume 7, pages 41-48.
  • Full Paper (Postscript, 8 pages, 79,983 bytes)
  • Abstract (Ascii text)
• Fr�d�ric Mayoraz, Thierry Cornu, and Laurent Vulliet.
  Using neural networks to predict slope movements.
  In Proceedings of the Seventh International Symposium on Landslides, Trondheim, Norway, June 1996. Pages 295-300. K. Senneset Ed., Balkema 1996.
  • Full Paper (Postscript, 6 pages, 42,791 bytes)
  • Abstract (Ascii text)
• Thierry Cornu, Paolo Ienne, Dagmar Niebur, and Marc A. Viredaz.
  A Systolic Accelerator for Power System Security Assessment.
  In A. Hertz, A. T. Holen, and J.-C. Rault, editors, Proceedings of the International Conference on Intelligent System Application to Power Systems, Montpellier, France, September 1994. Volume I, pages 431-38.
  • Full Paper (PostScript, 8 pages, 165,933 bytes)
  • Abstract (Ascii text)

Publications on Dedicated Hardware for Neural Networks

• Paolo Ienne Lopez.
  Programmable VLSI Systolic Processors for Neural Network and Matrix Computations.
  PhD Thesis no. 1525, Swiss Federal Institute of Technology, Lausanne, 1996.
  • Full thesis (PostScript, 160 pages, 700,112 bytes)
  • Abstract (Ascii text)
• Joan Cabestany, Paolo Ienne, Juan Manuel Moreno, and Jordi Madrenas.
  Is There a future for ANN Hardware?
  In Proceedings of the Workshop on Mixed Design of Integrated Circuits and Systems, Lodz, Poland, May 1996. To appear.
  • Full Paper (PostScript, 6 pages, 31,634 bytes)
  • Abstract (Ascii text)
• Paolo Ienne, Thierry Cornu, and Gary Kuhn.
  Special-Purpose Digital Hardware for Neural Networks: An Architectural Survey.
  Journal of VLSI Signal Processing. To appear.
  • Abstract (Ascii text)
• Thierry Cornu, Paolo Ienne, Dagmar Niebur, Patrick Thiran, and Marc A. Viredaz.
  Design, Implementation and Test of a Multi-Model Systolic Neural-Network Accelerator.
  Scientific Programming. Volume 5, no. 1, Spring 1996. Pages 47-61.
  • Full Paper (PostScript, 14 pages, 169,221 bytes)
  • Abstract (Ascii text)
• Paolo Ienne and Gary Kuhn.
  Digital Systems for Neural Networks.
  In P. Papamichalis and R. Kerwin, editors, Digital Signal Processing Technology, Volume 57 of Critical Review Series. SPIE Optical Engineering, Orlando, Fla., 1995. Pages 314-45.
  • Full Paper (A4 paper) (PostScript, 32 pages, 144,874 bytes)
  • Full Paper (US letter paper) (PostScript, 32 pages, 145,018 bytes)
  • Abstract (Ascii text)
• Paolo Ienne.
  Horizontal Microcode Compaction for Programmable Systolic Accelerators.
  In Peter Cappello, Catherine Mongenet, Guy-René Perrin, Patrice Quinton, and Yves Robert, editors, Proceedings of the International Conference on Application Specific Array Processors, Strasbourg, July 1995. Pages 85-92.
  • Full Paper (PostScript, 8 pages, 50,455 bytes)
  • Abstract (Ascii text)
• Paolo Ienne.
  Digital Hardware Architectures for Neural Networks.
  SPEEDUP Journal, June 1995. Volume 9, no. 1, pages 18-25.
  • Full Paper (PostScript, 7 pages, 79,396 bytes)
  • Abstract (Ascii text)
• Paolo Ienne and Marc A. Viredaz.
  Implementation of Kohonen's Self-Organizing Maps on MANTRA I.
  In Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, Turin, September 1994. Pages 273-79.
  • Full Paper (PostScript, 7 pages, 62,007 bytes)
  • Abstract (Ascii text)
• Thierry Cornu and Paolo Ienne.
  Performance of Digital Neuro-computers.
  In Proceedings of the Fourth International Conference on Microelectronics for Neural Networks and Fuzzy Systems, Turin, September 1994. Pages 87-93.
  • Full Paper (PostScript, 7 pages, 45,339 bytes)
  • Abstract (Ascii text)
• Marc A. Viredaz.
  Design and Analysis of a Systolic Array for Neural Computation.
  PhD Thesis no. 1264, Swiss Federal Institute of Technology, Lausanne, 1994.
  • Full thesis (PostScript, 201 pages, 1,250,621 bytes)
  • Abstract (English) (PostScript, 2 pages, 6,582 bytes)
  • Résumé (Français) (PostScript, 2 pages, 7,756 bytes)
• Paolo Ienne and Marc A. Viredaz.
  Bit-Serial Multipliers and Squarers.
  IEEE Transactions on Computers. Volume C-43, no. 12, December 1994, pages 1445-50.
  • Full Paper (PostScript, 15 pages, 69,620 bytes)
  • Abstract (Ascii text)
• Paolo Ienne and Marc A. Viredaz.
  GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator.
  Journal of VLSI Signal Processing. Volume 9, no. 3. Pages 257-73.
  • Full Paper (Hypertext)
• Marc A. Viredaz and Paolo Ienne.
  MANTRA I: A Systolic Neuro-Computer.
  In Proceedings of the International Joint Conference on Neural Networks, Nagoya, Japan, October 1993. Volume III, pages 3054-57.
  • Full Paper (PostScript, 4 pages, 42,273 bytes)
  • Abstract (Ascii text)
• Paolo Ienne and Marc A. Viredaz.
  GENES IV: A Bit-Serial Processing Element for a Multi-Model Neural-Network Accelerator.
  In Luigi Dadda and Benjamin Wah, editors, Proceedings of the International Conference on Application Specific Array Processors, Venezia, October 1993. Pages 345-56.
  • Full Paper (PostScript, 12 pages, 82,038 bytes)
  • Abstract (Ascii text)
• Paolo Ienne.
  Quantitative Comparison of Architectures for Digital Neuro-Computers.
  In Proceedings of the International Joint Conference on Neural Networks, Nagoya, Japan, October 1993. Volume II, pages 1987-90.
  • Full Paper (PostScript, 4 pages, 42,394 bytes)
  • Abstract (Ascii text)
• Marc A. Viredaz.
  MANTRA I: An SIMD Processor Array for Neural Computation.
  In Peter Paul Spies, editor, Proceedings of the Euro-ARCH'93 Conference, M�nchen, October 1993. Pages 99-110.
  • Full Paper (PostScript, 12 pages, 2,923,663 bytes)
  • Full Paper, no photographs (PostScript, 12 pages, 81,315 bytes)
  • Abstract (Ascii text)
• Marc A. Viredaz, Christian Lehmann, Fran�ois Blayo, and Paolo Ienne.
  MANTRA: A multi-model neural-network computer.
  In Jos� G. Delgado-Frias and William R. Moore, editors, VLSI for Neural Networks and Artificial Intelligence. Plenum Press, New York, 1994. Pages 93-102.
  • Not available in electronic form
• Christian Lehmann, Marc Viredaz, and Francois Blayo.
  A Generic Systolic Array Building Block for Neural Networks with On-Chip Learning
  IEEE Transactions on Neural Networks. Volume 4, no. 3, May 1993, pages 400-407.
  • Paper not available in electronic form
  • Abstract (Ascii text)

Publications on Theoretical Issues

• Paolo Ienne, Patrick Thiran, and Nikolaos Vassilas.
  Modified Self-Organizing Feature Map Algorithms for Efficient Digital Hardware Implementation. IEEE Transactions on Neural Networks. To appear.
  • Abstract (Ascii text)
• Nikolaos Vassilas, Patrick Thiran, and Paolo Ienne.
  On modifications of Kohonen's feature map algorithm for an efficient parallel implementation. In Proceedings of the International Conference on Neural Networks, Washington, D.C., June 1996. Volume II, pages 932-37.
  • Full Paper (PostScript, 6 pages, 63,596 bytes)
  • Abstract (Ascii text)
• Christian Lehmann and Marie Cottrell.
  A New Approach to Stochastic Integrate-and-Fire Neurone Modelling.
  MANTRA Internal Report no. 94/4.
  • Not available in electronic form
• Patrick Thiran, Vincent Peiris, Pascal Heim, and Bertrand Hochet.
  Quantization Effects in Digitally Behaving Circuit Implementations of Kohonen Networks.
  IEEE Transactions on Neural Networks, May 1994. Volume 5, no.3, pages 450-58.
  • Not available in electronic form
• Christian Lehmann and Marie Cottrell.
  S.L.I.F.: Un mod�le stochastique d'une population de neurones.
  In Neurosciences et sciences de l'ing�nieur, Chamonix, France, May 1994.
  • Not available in electronic form
• Christian Lehmann.
  Self-Organisation of Large Feature Maps using Local Computations: Analysis and VLSI Integration.
  In Stan Gielen and Bert Kappen, editors, Proceedings of International Conference on Artificial Neural Networks, Amsterdam, September 1993. Page 1082.
  • Paper not available in electronic form
  • Abstract (Ascii text)
• Christian Lehmann.
  R�seaux de neurones comp�titifs de grandes dimensions pour l'auto-organisation: analyse, synth�se et implantation sur circuits systoliques.
  PhD Thesis no. 1129, Swiss Federal Institute of Technology, Lausanne, 1993.
  • Paper not available in electronic form
  • Abstract (Ascii text)

Publications on Programming Environments for Neural Networks

• Thierry Cornu and Stephane Vialle.
  A Framework for Implementing Highly Parallel Applications on Distributed Memory Architectures.
  To appear in J. R. Davy and P. M. Dew, editors, Abstract Machine Models for Highly Parallel Computers, Oxford University Press.
  • Full Paper (PostScript, 24 pages, 73,728 bytes)
  • Abstract (Ascii text)
• Yannick Lallement, Thierry Cornu, and Stephane Vialle.
  An Abstract Machine for Implementing Connectionist and Hybrid Systems on Multi-processor Architectures.
  In H. Kitano, V. Kumar and C. B. Suttner, editors, Parallel Processing for Artificial Intelligence 2, Machine Intelligence and Pattern Recognition series, Elsevier Science, June 1994.
  • Full Paper (PostScript, 17 pages, 59,566 bytes)
  • Abstract (Ascii text)

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