Conference papers

2019

Composite Data Types in Dynamic Dataflow Languages as Copyless Memory Sharing Mechanism

A. Bloch; E. Bezati; M. Mattavelli 

2019-06-08. Computational Science – ICCS 2019. p. 717-724. DOI : 10.1007/978-3-030-22750-0_70.

Modeling Dielectric Constant Variability in Aggregate Polymers from CV Measurements

R. M. Dos Santos; C. Dehollain; M. Mattavelli; D. Barrettino; J-M. Sallese 

2019-01-01. Latin American Electron Devices Conference (LAEDC), Armenia, Colombia, February 24-27, 2019. p. 100-103.

Toward a Dynamic Threshold for Quality-Score Distortion in Reference-Based Alignment

A. A. Hernandez-Lopez; C. Alberti; M. Mattavelli 

2019. 15th International Symposium on Bioinformatics Research and Applications (ISBRA), Barcelona, Spain, June 3–6, 2019.

2018

Shared-variable Synchronization Approaches for Dynamic Data Flow Programs

A. Modas; S. Casale-Brunet; R. Stewart; E. Bezati; J. Ahmad et al. 

2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 263-268.

Efficient Dynamic Optimisation Heuristics for Dataflow Pipelines

A. Prihozhy; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2018-01-01. IEEE International Workshop on Signal Processing Systems (IEEE SiPS), Cape Town, SOUTH AFRICA, Oct 21-24, 2018. p. 337-342.

High Precision Capacitive Moisture Sensor for Polymers

R. M. Dos Santos; J-M. Sallese; M. Mattavelli; C. Dehollain; D. Barrettino 

2018-01-01. 17th IEEE SENSORS Conference, New Delhi, INDIA, Oct 28-31, 2018. p. 212-215.

Lossy compression of quality scores in differential gene expression: A first assessment and impact analysis

A. A. Hernandez Lopez 

2018. Data compression conference (DCC) , Snowbird, Utah, March 27-30, 2018.

2017

Design space exploration of dataflow-based Smith-Waterman FPGA implementations, 2017 IEEE International Workshop on Signal Processing Systems (SiPS)

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2017-10-03. Signal Processing Systems (SiPS), 2017 IEEE International Workshop on. p. 1-6. DOI : 10.1109/SiPS.2017.8109982.

Performance estimation of program partitions on multi-core platforms, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

M. Michalska; J. J. Ahmad; E. Bezati; S. Casale-Brunet; M. Mattavelli 

2017-09-21.  p. 1-8. DOI : 10.1109/PATMOS.2016.7833418.

Buffer dimensioning for throughput improvement of dynamic dataflow signal processing applications on multi-core platforms

M. Michalska; E. Bezati; S. Casale-Brunet; M. Mattavelli 

2017-08-28.  p. 1339-1343. DOI : 10.23919/EUSIPCO.2017.8081426.

High level synthesis of Smith-Waterman dataflow implementations

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2017-03-05.  p. 1173-1177. DOI : 10.1109/ICASSP.2017.7952341.

Real-Time Monitoring of the Hydration Level by Multi-Frequency Bioimpedance Spectroscopy

D. Allegri; D. Vaca; D. Ferreira; M. Rogantini; D. R. Barrettino 

2017. IEEE International Instrumentation and Measurement Technology Conference, Torino, Italy, May 22-25, 2017. p. pp. 1-6.

MPEG-G the emerging standard for genomic data compression

M. Hernaez; C. Alberti; M. Mattavelli; I. Ochoa 

2017. Rocky 2017 Bioinformatics Conference, Aspen, Colorado, USA, December 7-9, 2017.

Differential gene expression with lossy compression of quality scores in RNA-seq data

A. A. Hernandez-Lopez; J. Voges; C. Alberti; M. Mattavelli; J. Ostermann 

2017. Data Compression Conference (DCC), Snowbird, UT, APR 04-07, 2017. p. 444-444. DOI : 10.1109/Dcc.2017.75.

2016

Trace-based manycore partitioning of stream-processing applications

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. Janneck 

2016-11-06.  p. 422-426. DOI : 10.1109/ACSSC.2016.7869073.

High-level system synthesis and optimization of dataflow programs for MPSoCs

E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck 

2016-11-06.  p. 417-421. DOI : 10.1109/ACSSC.2016.7869072.

Design Space Exploration Problem Formulation for Dataflow Programs on Heterogeneous Architectures, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

M. Michalska; N. Zufferey; E. Bezati; M. Mattavelli 

2016-09-21.  p. 217-224. DOI : 10.1109/MCSoC.2016.25.

Programming Models and Methods for Heterogeneous Parallel Embedded Systems, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

S. Casale-Brunet; E. Bezati; M. Mattavelli 

2016-09-21.  p. 289-296. DOI : 10.1109/MCSoC.2016.39.

High-Precision Performance Estimation of Dynamic Dataflow Programs, 2016 IEEE 10th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSOC)

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2016-09-21.  p. 101-108. DOI : 10.1109/MCSoC.2016.23.

High-level synthesis of dynamic dataflow programs on heterogeneous MPSoC platforms

E. Bezati; S. Casale-Brunet; M. Mattavelli; J. W. Janneck 

2016-07-17.  p. 227-234. DOI : 10.1109/SAMOS.2016.7818352.

An Evaluation Framework for Lossy Compression of Genome Sequencing Quality Values

C. Alberti; N. Daniels; M. Hernaez; J. Voges; R. L. Goldfeder et al. 

2016. IEEE Data Compression Conference 2016, Snowbird, Utah, USA, DOI : 10.1109/Dcc.2016.39.

2015

H2B2VS (HEVC Hybrid Broadcast Broadband Video Services) – building innovative solutions over hybrid networks

R. Monnier; A. Mourelle; J-P. Bernoux; C. Alberti; J. Le Feuvre et al. 

2015. International Broadcasting Conference 2015, Amsterdam, September 11, 2015.

A Methodology for Profiling and Partitioning Stream Programs on Many-core Architectures

M. Michalska; J. Boutellier; M. Mattavelli 

2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 2962-2966. DOI : 10.1016/j.procs.2015.05.498.

Execution Trace Graph Based Multi-criteria Partitioning of Stream Programs

M. Michalska; S. Casale-Brunet; E. Bezati; M. Mattavelli 

2015. International Conference on Computational Science (ICCS), Reykjavik, Iceland, June 1-3, 2015. p. 1443-1452. DOI : 10.1016/j.procs.2015.05.334.

2014

TURNUS: an open-source design space exploration framework for dynamic stream programs

S. Casale Brunet; M. Michalska; E. Bezati; M. Mattavelli; J. Janneck et al. 

2014. Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, October 2014.

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling

M. Canale; S. Casale Brunet; E. Bezati; M. Mattavelli; J. Janneck 

2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, October 2014.

MPEG high efficient video coding stream programming and many-cores scalability

D. J. De Saint Jorre; D. Renzi; S. Casale Brunet; M. Michalska; E. Bezati et al. 

2014. 

TURNUS: An open-source design space exploration framework for dynamic stream programs

S. Casale-Brunet; M. Wiszniewska; E. Bezati; M. Mattavelli; J. W. Janneck et al. 

2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-2. DOI : 10.1109/DASIP.2014.7115614.

Execution trace graph analysis of dataflow programs: Bounded buffer scheduling and deadlock recovery using model predictive control

S. Casale-Brunet; E. Bezati; M. Mattavelli; M. Canale; J. W. Janneck 

2014. 2014 Conference on Design and Architectures for Signal and Image Processing (DASIP), Madrid, Spain, 8-10 October 2014. p. 1-6. DOI : 10.1109/DASIP.2014.7115623.

Coarse grain clock gating of streaming applications in programmable logic implementations

E. Bezati; S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2014. 2014 Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, USA, 31 May - 1 June 2014. p. 1-6. DOI : 10.1109/ESLsyn.2014.6850387.

Characterizing communication behavior of dataflow programs using trace analysis

J. W. Janneck; S. Casale-Brunet; M. Mattavelli 

2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 44-50. DOI : 10.1109/SAMOS.2014.6893193.

Exploring MPEG HEVC decoder parallelism for the efficient porting onto many-core platforms

D. De Saint Jorre; C. Alberti; M. Mattavelli; S. Casale-Brunet 

2014. 2014 IEEE International Conference on Image Processing (ICIP), Paris, France, 27-30 October 2014. p. 2115-2119. DOI : 10.1109/ICIP.2014.7025424.

Dataflow machines

J. W. Janneck; G. Cerdersjo; E. Bezati; S. C. Brunet 

2014. 2014 48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA, 2-5 November 2014. p. 1848-1852. DOI : 10.1109/ACSSC.2014.7094788.

Dataflow programs analysis and optimization using model predictive control techniques: An example of bounded buffer scheduling

M. Canale; S. Casale-Brunet; E. Bezati; M. Mattavelli; J. W. Janneck 

2014. 2014 IEEE Workshop on Signal Processing Systems (SiPS), Belfast, United Kingdom, 20-22 October 2014. p. 1-6. DOI : 10.1109/SiPS.2014.6986054.

Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case

C. Sau; L. Raffo; F. Palumbo; E. Bezati; S. Casale-Brunet et al. 

2014. 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Samos, Greece, 14-17 July 2014. p. 59-66. DOI : 10.1109/SAMOS.2014.6893195.

Coarse Grain Clock Gating Of Streaming Applications In Programmable Logic Implementations

E. Bezati; S. C. Brunet; M. Mattavelli; J. W. Janneck 

2014. 4th Electronic System Level Synthesis Conference (ESLsyn), San Francisco, CA, MAY 31-JUN 01, 2014.

A Methodology For Optimizing Buffer Sizes Of Dynamic Dataflow Fpgas Implementations

A. A-H. Ab Rahman; S. Casale-Brunet; C. Alberti; M. Mattavelli 

2014. IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Florence, ITALY, MAY 04-09, 2014.

ECMA-407: A New 3D audio codec implementation up to NHK 22.2

J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. 

2014. The 28th VDT International Convention 2014.

ECMA-407: New Approaches to 3D Audio Content Data Rate Reduction with RVC-CAL

J. J. Ahmad; C. Alberti; J. Hong; B. Leonard; M. Mattavelli et al. 

2014. 137th International Audio Engineering Society (AES) Convention, Los Angeles, California, USA, October 9-12, 2014.

2013

Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.

Modeling Control Tokens for Composition of CAL Actors

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli 

2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS

J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius 

2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624.

Systems Design Space Exploration by Serial Dataflow Program Executions

S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.

Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study

A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli 

2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

Porting an MPEG-HEVC decoder to a low-power many-core platform

D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

E. Bezati; M. Mattavelli; J. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.

A Lego Mindstorms NXT Experiment for Model Predictive Control Education

M. Canale; S. Casale Brunet 

2013. European Control Conference, Zurich, Switzerland, 2013.

Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework

S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

TURNUS: A design exploration framework for dataflow system design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.

Synthesis and optimization of high-level stream programs

E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck 

2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.

Buffer optimization based on critical path analysis of a dataflow program design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.

Live demonstration: High level software and hardware synthesis of dataflow programs

E. Bezati; G. Roquier; M. Mattavelli 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.

Performance Benchmarking of RVC based Multimedia Specifications

J. J. Ahmad; S. Li; M. Mattavelli 

2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.

TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.

Representing Guard Dependencies in Dataflow Execution Traces

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.

Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.

2012

Scheduling of dynamic dataflow programs based on state space analysis

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli 

2012. IEEE International Conference on Acoustics, Speech and Signal Processing, Kyoto, Japan, March 25-30, 2012. p. 1661-1664.

Using Scalable Video Coding For Dynamic Adaptive Streaming Over HTTP in Mobile Environments

C. Müller; D. Renzi; S. Lederer; S. Battista; C. Timmerer 

2012. EUSIPCO12, Bucharest, Romania, 2012.08.31. p. 2208-2212.

Distributed Adaptation Decision-Taking Framework and Scalable Video Coding Tunneling for Edge and In-Network Media Adaptation

M. Grafl; C. Timmerer; M. Waltl; D. Renzi; S. Battista et al. 

2012. TEMU 2012, Heraklion, Greece, July 31, 2012. p. 6. DOI : 10.1109/TEMU.2012.6294710.

Profiling of Dataflow Programs Using Post Mortem Causation Traces

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2012. 2012 IEEE Workshop on Signal Processing Systems (SiPS), Quebec City, QC, Canada, 17-19 October 2012. p. 220-225. DOI : 10.1109/SiPS.2012.54.

Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program

A. Rahman; A. A. H. Bin; R. Thavot; S. Casale Brunet; E. Bezati et al. 

2012. 2012 Conference on Design and Architectures for Signal and Image Processing, Karlsruhe, Germany, 25 October 2012.

2011

Methodology For The Hardware/Software Co-Design Of Dataflow Programs

G. Roquier; R. Thavot; M. Mattavelli 

2011. IEEE Workshop on Signal Processing Systems (SiPS), Beirut, LEBANON, Oct 04-07, 2011. p. 174-179. DOI : 10.1109/SiPS.2011.6088970.

Portable and scalable parallelism for multi-core and reconfigurable hardware using dataflow programs

G. Roquier; E. Benzati; M. Mattavelli; J. W. Janneck 

2011. MCC2011, Fourth Swedish Workshop on Multicore Computing, Linköping, Sweden, November 23-25, 2011.

Building Multimedia Security Applications in the MPEG Reconfigurable Video Coding (RVC) Framework

J. J. Ahmad; S. Li; I. Amer; M. Mattavelli 

2011. 13th ACM WS on Multimedia and Security, Buffalo, NY, USA, Sept 29-30, 2011. p. 121-130.

Hardware/Software Co-Design of Dataflow Programs for Reconfigurable Hardware and Multi-Core Platforms

G. Roquier; E. Bezati; R. Thavot; M. Mattavelli 

2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, Nov 2-4, 2011.

A Unified Hardware/Software Co-Synthesis Solution for Signal Processing Systems

E. Bezati; H. Yviquel; M. Raulet; M. Mattavelli 

2011. DASIP 2011, Conference on Design and Architectures for Signal and Image Processin, Tampere, Finland, Nov 2-4, 2011.

Optimization of Portable Parallel Signal Processing Applications by Design Space Exploration of Dataflow Programs

C. Lucarz; M. Mattavelli; J. Janneck 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct. 4-7, 2011.

Scheduling of Dynamic Dataflow Programs with Model Checking

J. Ersfolk; G. Roquier; F. Jokhio; J. Lilius; M. Mattavelli 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut, Lebanon, Oct. 4-7, 2011.

Methodology for the Hardware/Software Co-Design of Dataflow Programs

G. Roquier; R. Thavot; M. Mattavelli 

2011. SIPS 2011, IEEE WS on Signal processing Systems, Beirut Lebanon, Oct.4-7, 2011.

Optimization Methodologies for Complex FPGA-based Signal Processing Systems with CAL

A. Rahman; A. A. H. Bin; H. Amer; A. Prihozhy; C. Lucarz et al. 

2011. 2011 Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, November 2-4, 2011.

Methodology and Technique to Improve Throughput of FPGA-based CAL Dataflow Programs: Case Study of the RVC MPEG-4 SP Intra Decoder

H. Amer; A. Rahman; A. A. H. Bin; I. Amer; C. Lucarz et al. 

2011. 2011 IEEE Workshop on Signal Processing Systems, Beirut, Lebanon, October 4-7, 2011.

2010

Hardware and Software Synthesis of Image Filters From CAL Dataflow Specification

A. Rahman; A. A. H. Bin; R. Thavot; M. Mattavelli; P. Faure 

2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.

Automatic mutli-connectivity interface generation for system designs based on a dataflow description

R. Thavot; A. Rahman; A. A. H. Bin; R. Mosqueron; M. Mattavelli 

2010. PRIME 2010, Berlin Institute of Technology, Germany, 18–21 July 2010.

High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms

C. Lucarz; G. Roquier; M. Mattavelli 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding

E. Bezati; M. Mattavelli; M. Raulet 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP 2010, Edinburgh, October 26-28, 2010.

RVC: a Multi-Decoder CAL Composer tool

F. Palumbo; D. Pani; E. Manca; L. Raffo; M. Mattavelli et al. 

2010. Conference on Design and Architectures for Signal and Image Processing, DASIP, Edinburgh, October 26-28, 2010.

Reconfigurable Video Coding — a Stream Programming Approach to the Specification of New Video Coding Standards

J. W. Jannek; M. Mattavelli; M. Raulet; M. Wipliez 

2010. MMSYS 2010, Phoenix, AZ, USA, Feb. 22-23, 2010.

An adaptive system for real-time scalable video streaming with end- to-end qos control

B. Shao; D. Renzi; P. Amon; G. Xilouris; N. Zotos et al. 

2010. The 11th International Workshop on Image Analysis for Multimedia Interactive Services (WIAMIS), Desenzano del Garda, Italy, Apr 12 - 14, 2010.

2009

Hardware synthesis of complex standard interfaces using CAL dataflow descriptions

R. Thavot; R. Mosqueron; J. Dubois; M. Mattavelli 

2009. DASIP, Sophia Antipolis, September 22-24, 2009.

Multiprocessor scheduling of dataflow models within the Reconfigurable Video Coding framework

J. Boutellier; V. Martin Gomez; O. Silven; C. Lucarz; M. Mattavelli 

2009. Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France, September 22 - 24, 2009.

Motion estimation accelerator with user search strategy for the RVC framework

J. Dubois; M. Mattavelli; J. Miteran; C. Lucarz; R. Mosqueron 

2009. IEEE International Conference on Image Processing, Cairo, Egypt, November 7-10, 2009.

Towards a Comprehensive RVC VTL: A CAL Description of an Efficient AVC Baseline Encoder

H. Aman-Allah; E. Hanna; K. Maarouf; I. Amer 

2009. IEEE International Conference on Image Processing, Special Session on Reconfigurable Video Coding, Cairo, Egypt, November 2009.

An MPEG RVC AVC Baseline Encoder Based on a Novel Iterative Methodology

H. Aman-Allah; E. Hanna; K. Maarouf; I. Amer 

2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.

MPEG RVC Compliant Intra Prediction for AVC

K. Maarouf; I. Amer 

2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.

AVC Entropy Coding for MPEG Reconfigurable Video Coding

H. Aman-Allah; I. Amer 

2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis, France, September 2009.

Towards a Multi-Granular RVC VTL: A Case Study of CAL Transformations on the ISO/IEC MPEG Fixed Point IDCT

I. Amer 

2009. ECSI Conference on Design and Architectures for Signal and Image Processing, Sophia Antipolis,France, September 2009.

An integrated environment for HW/SW co-design based on a CAL specification and HW/SW code generators

G. Roquier; C. Lucarz; M. Mattavelli; M. Wipliez; M. Raulet et al. 

2009. ISCAS 2009, Taipei, Taiwan, May, 2009. p. 799-799.

Reconfigurable Video Coding : Objectives and Technologies

C. Lucarz; I. Amer; M. Mattavelli 

2009. IEEE International Conference on Image Processing, Cairo, Egypt: 2009, Cairo, Egypt, 7-10 November, 2009. p. 749-752.

2008

Video Decoder Reconfigurations and AVS Extensions in the New MPEG Reconfigurable Video Coding Framework

D. Ding; L. Yu; C. Lucarz; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

Scheduling Of Dataflow Models Within The Reconfigurable Video Coding Framework

J. Boutellier; V. Sadhanala; C. Lucarz; P. Brisk; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems. SiPS 2008. , Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

Validation of Bitstream Syntax and Synthesis of Parsers in the MPEG Reconfigurable Video Coding Framework

M. Raulet; J. Piat; C. Lucarz; M. Mattavelli 

2008. IEEE Workshop on Signal Processing Systems, Washington, D.C. Metro Area, U.S.A, October 8-10, 2008.

OpenDF - A Dataflow Toolset for Reconfigurable Hardware and Multicore Systems

S. Bhattacharyya; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. 

2008. First Swedish Workshop on Multi-Core Computing, MCC, Ronneby, Sweden, November 27-28, 2008.

Translating Dataflow Programs to Efficient Hardware: an MPEG-4 Simple Profile Decoder Case Study

J. W. Janneck; I. D. Miller; D. B. Parlour; M. Mattavelli; C. Lucarz et al. 

2008. Design, Automation and Test in Europe (DATE), Munich, Germany, 2008.

A co-design platform for Algorithm/Architecture design exploration

C. Lucarz; M. Mattavelli; J. Dubois 

2008. IEEE International Conference on Multimedia & Expo, Hannover, Germany, June 23-26, 2008.

A Multimedia Terminal for Adaptation and End-to-end QoS Control

B. Shao; M. Mattavelli; D. Renzi; M. Andrade; S. Battista et al. 

2008. IEEE International Conference on Multimedia & Expo (ICME 2008), Hannover, Germany, June 23-26, 2008.

How to Make Stream Processing More Mainstream

B. Shuvra; G. Brebner; J. Eker; J. Janneck; M. Mattavelli et al. 

2008. Workshop on Streaming Systems: From Web and Enterprise to Multicore, in conjunction with the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Como, Italy, November 8, 2008.