Publications 2013

Optimizing Dataflow Programs for Hardware Synthesis

A. A. H. B. Ab Rahman / M. Mattavelli (Dir.)  

Lausanne: EPFL, 2014. DOI : 10.5075/epfl-thesis-6059.

Automated Qoe Evaluation Of Dynamic Adaptive Streaming Over Http

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. 5th International Workshop on Quality of Multimedia Experience (QoMEX). p. 58-63.

Partitioning And Optimization Of High Level Stream Applications For Multi Clock Domain Architectures

S. C. Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. IEEE Workshop on Signal Processing Systems (SiPS). p. 177-182.

Methods to explore design space for MPEG RMC codec specifications

S. Casale-Brunet; A. Elguindy; E. Bezati; R. Thavot; G. Roquier et al. 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1278-1294. DOI : 10.1016/j.image.2013.08.012.

Reconfigurable media coding: An overview

E. S. Jang; M. Mattavelli; M. Preda; M. Raulet; H. Sun 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1215-1223. DOI : 10.1016/j.image.2013.08.008.

Modeling Control Tokens for Composition of CAL Actors

J. Ersfolk; G. Roquier; J. Lilius; M. Mattavelli 

2013. Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

STATIC AND QUASI-STATIC COMPOSITIONS OF STREAM PROCESSING APPLICATIONS FROM DYNAMIC DATAFLOW PROGRAMS

J. Ersfolk; G. Roquier; W. Lund; M. Mattavelli; J. Lilius 

2013. IEEE International Conference on Acoustics, Speech and Signal Processing, Vancouver, Canada, May 26-31, 2013. p. 2620-2624.

Systems Design Space Exploration by Serial Dataflow Program Executions

S. Casale Brunet; C. Alberti; M. Mattavelli; J. Janneck 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Multi-clock domain optimization for reconfigurable architectures in high-level dataflow applications

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, CA, USA, 3-6 November, 2013.

Partitioning and Optimization of high level Stream applications for Multi Clock Domain Architectures

S. Casale Brunet; E. Bezati; C. Alberti; M. Mattavelli; E. Amaldi et al. 

2013. Signal Processing Systems (SiPS), Taipei, Taiwan, 16-18 October, 2013.

Dataflow Program Analysis and Refactoring Techniques for Design Space Exploration: MPEG-4 AVC/H.264 Decoder Implementation Case Study

A. Rahman; A. A. H. Bin; S. Casale Brunet; C. Alberti; M. Mattavelli 

2013. Design & Architectures for Signal & Image Processing (DASIP), Cagliari, Italy, October 8-10, 2013.

Porting an MPEG-HEVC decoder to a low-power many-core platform

D. S. Jorre; D. Jack; C. Alberti; M. Mattavelli; S. Casale Brunet 

2013. Asilomar Conference on Signals, Systems, and Computers, Pacific Grove, California, USA, November 3-6th, 2013.

High-Level Synthesis of Dataflow Programs for Signal Processing Systems

E. Bezati; M. Mattavelli; J. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis (ISPA 2013), Trieste, Italy, 4-6, September 2013.

Scalable Media Coding Enabling Content-Aware Networking

M. Grafl; C. Timmerer; H. Hellwagner; G. Xilouris; G. Gardikis et al. 

IEEE Multimedia. 2013. Vol. 20, num. 2, p. 30-41. DOI : 10.1109/MMUL.2012.57.

A Lego Mindstorms NXT Experiment for Model Predictive Control Education

M. Canale; S. Casale Brunet 

2013. European Control Conference, Zurich, Switzerland, 2013.

Design Space Exploration and Implementation of RVC-CAL Applications using the TURNUS framework

S. Casale Brunet; E. Bezati; G. Roquier; C. Alberti; M. Mattavelli et al. 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

TURNUS: A design exploration framework for dataflow system design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 654-654. DOI : 10.1109/ISCAS.2013.6571927.

Synthesis and optimization of high-level stream programs

E. Bezati; S. Casale Brunet; M. Mattavelli; J. Janneck 

2013. lectronic System Level Synthesis Conference (ESLsyn), Austin, Texas, USA, May 31 2013-June 1 2013.

Buffer optimization based on critical path analysis of a dataflow program design

S. Casale Brunet; M. Mattavelli; J. W. Janneck 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 19-23 05 2013. p. 1384-1387. DOI : 10.1109/ISCAS.2013.6572113.

Live demonstration: High level software and hardware synthesis of dataflow programs

E. Bezati; G. Roquier; M. Mattavelli 

2013. 2013 IEEE International Symposium on Circuits and Systems (ISCAS),, Beijing, China, 19-23 May 2013. DOI : 10.1109/ISCAS.2013.6571930.

Secure Computing with the MPEG RVC Framework

J. J. Ahmad; S. Li; R. Thavot; M. Mattavelli 

Signal Processing-Image Communication. 2013. Vol. 28, num. 10, p. 1315-1334. DOI : 10.1016/j.image.2013.08.015.

Performance Benchmarking of RVC based Multimedia Specifications

J. J. Ahmad; S. Li; M. Mattavelli 

2013. 20th IEEE International Conference on Image Processing (ICIP), Melbourne, Australia, September 15-18, 2013.

TURNUS: a unified dataflow design space exploration framework for heterogeneous parallel systems

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. Conference on Design & Architectures for Signal & Image Processing, Cagliari, Italy, 8-10 October 2013.

Design Space Exploration of High Level Stream Programs on Parallel Architectures: A focus on the Buffer Size Minimization and Optimization Problem

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 8th International Symposium on Image and Signal Processing and Analysis, Trieste, Italy, 4-6 September 2013.

Representing Guard Dependencies in Dataflow Execution Traces

S. Casale Brunet; M. Mattavelli; C. Alberti; J. W. Janneck 

2013. 2013 Fifth International Conference on Computational Intelligence, Communication Systems and Networks (CICSyN), Madrid, Spain, 5-7 06 2013. p. 291-295. DOI : 10.1109/CICSYN.2013.26.

Automated QoE Evaluation of Dynamic Adaptive Streaming over HTTP

C. Alberti; D. Renzi; C. Timmerer; C. Mueller; S. Lederer et al. 

2013. Fifth International Workshop on Quality of Multimedia Experience (QoMEX), Klagenfurt, Austria, July 3-5, 2013.

HAWK: an open error-control and cryptographic V-VLIW processor for digital communication techniques and storage

J. T. Randriamalazarivo / D. Mlynek (Dir.)  

Lausanne: EPFL, 1999. DOI : 10.5075/epfl-thesis-2013.